Browse Prior Art Database

Modeling of Storage Elements in Terms of the Timing of Their Component Parts

IP.com Disclosure Number: IPCOM000050519D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 4 page(s) / 35K

Publishing Venue

IBM

Related People

Cheng, DD: AUTHOR [+4]

Abstract

This is article is related to information contained in other articles on pages 2819-2820 and 2826-2830 of this issue.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 43% of the total text.

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Modeling of Storage Elements in Terms of the Timing of Their Component Parts

This is article is related to information contained in other articles on pages 2819-2820 and 2826-2830 of this issue.

To properly analyze the timing of a computer logic graph, it is necessary to identify the storage elements and recognize the special function they provide.

In Part 1 there is described the important function the storage elements play and some data required to allow an individual to analyze that function. In Part 2 there is discussed a method for modeling a storage element in terms of the function performed by its individual parts.

In both parts, it is assumed that the storage elements are coded as single blocks with unique and recognizable functions. Part 1 - The Storage Element Function

A. The Model - We model the logic as a collection of blocks (figure), each block with a certain number of input nets and output nets, with certain blocks
(i.e., latches, triggers, registers, etc.) designated as storage elements (SEs), and with certain input nets identified as clock nets. The nets connected to blocks for which at least one source is not in the modeled logic are called Primary Input (PI) nets; those which originate within the logic and feed blocks not in the logic are Primary Output (PO) nets.

The Storage Elements are controlled by the clocks which are connected to them. To see how this control takes place, for each SE, we need a description of the clock controlling it. The appropriate clock times are defined at the Primary Inputs - the program propagates them to the SEs, delaying them as they pass through the combinational logic.

For each clock we need two sampling regions: the first for propagating signals from an SE, and the second for comparing with signals which arrive at the SE. The user knows the clock interrelationships and can select a consistent set of times for propagation and comparison. (See the figure).

For all blocks we require delay information, as well as the dependency of the output signal when rising (falling) on the rising or falling input signals, and the corresponding delays through the block. For the Storage Elements we also need information regarding the minimum time required for a signal causing a rise (fall) to overlap with the trailing portion of a clock to guarantee that the signal will latch, and the maximum overlap with the trailing portion of a clock that will be ignored.

If the given logic spans much of a multilevel physical package, we will also need the time of flight delay for each net, i.e., the delay from the source to each sink in the net. Additionally, the time when a rising (falling) signal is to start at a Primary Input or is required to be at a Primary Output may be given, in which case the system will use these times at the start of propagation and at the comparison phase respectively.

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B. The Use Of Storage Elements To Do Tests - Once we accept that the SE reference times have been est...