Browse Prior Art Database

Increased Valid Data Readout Time in Static RAM

IP.com Disclosure Number: IPCOM000050534D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Lawrence, JA: AUTHOR

Abstract

Adding a secons, cascaded output latch on each bit line of a static FET (field-effect transistor) read/write RAM (random-access memory) array greatly increases the proportion of the RAM cycle time during which the output data line is valid for reading by external circuits.

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Increased Valid Data Readout Time in Static RAM

Adding a secons, cascaded output latch on each bit line of a static FET (field-effect transistor) read/write RAM (random-access memory) array greatly increases the proportion of the RAM cycle time during which the output data line is valid for reading by external circuits.

A conventional rectangular array of six-device memory cells 10 (Fig. 1) has enhancement FETs Q11-Q14 and depletion FETs Q13-Q16 inter-connected by word lines 11 and by complementary bit lines 12, 12'. Each bit line to be output sets or resets a conventional latch 20, having FETs Q21-Q28 and complementary output lines 21, 21'. Latch 20 is set or reset when the -READ CLOCK signal on line 22 is high.

Instead of taking the RAM read data directly from latch 20, lines 21, 21' set or reset another latch 30, having FETs Q31-Q38 and complementary output lines 31, 31' which drive output buffer 40, having FETs Q41-Q42 and a single read- data output line 41. Latch 30 is set or reset by a high +READ clock signal on line
32. That is, latch 30 is out of phase with latch 20.

Fig. 2 shows the latch timings. Output 21 of latch 20, which would be the read-data output of a conventional RAM, is valid only about half the total cycle duration. The addition of latch 30 causes read-data output 41 to be valid during the entire cycle time except for the relatively small switching interval of latch 30.

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