Browse Prior Art Database

Three Terminal, Four Device CMOS Static RAM Cell

IP.com Disclosure Number: IPCOM000050571D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Chappell, BA: AUTHOR

Abstract

A three terminal, four-device CMOS static RAM (random-access memory) cell is described. This CMOS cell offers a density approaching the density obtainable with an NMOS RAM cell while offering the robust, low-power standby state of a larger six-device CMOS cell.

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Three Terminal, Four Device CMOS Static RAM Cell

A three terminal, four-device CMOS static RAM (random-access memory) cell is described. This CMOS cell offers a density approaching the density obtainable with an NMOS RAM cell while offering the robust, low-power standby state of a larger six-device CMOS cell.

A schematic of the three-terminal, four-device CMOS static RAM is shown in Fig. 1. Case 1 (Fig. 1A) and case 2 (Fig. 1B) are dual versions of the cell with exactly opposite operation. What is described here is that this relatively compact cell can be used to achieve fully static, low power latching of the standby state by using a dynamic read operation.

A specific example of the operation of the case 1 cell is shown in Fig. 2. The operation of the cell is such that in standby, it provides CMOS static latching of the stored state; in other words, there is a path to ground holding down the low node, but there is no DC current path. This is accomplished by taking both bitlines to ground and the wordline to VDD. During an active cycle, all cells are deselected by lowering all wordlines to an intermediate voltage that cuts off the n-devices but leaves enough potential between the latch nodes to retain the state of a cell. This implies that the threshold of the n-devices should be greater than the p-device threshold by some margin that is a function of the details of the design (a factor of two should be more than sufficient). Consequently, an extra mask may be needed to selectively shift the thresholds in the array.

While the wordlines are deselected, the bitlines are preconditioned. In the case of a read, this consists of taking both bitlines to VDD; for a write, one bitline is tied to VDD, the other to ground. The deselection of the wordlines and the charging of the bitlines can take place while the address inputs are being detected and decoded. After decoding, the selected wordline is returned to VDD; note that no DC current sink is required to select the wordline.

For the case of a read, as the wordline is charged to VDD, one of the n- devices will conduct charge from the bitline capacitance to the internal capacitance of the cell. This is analogous to the operation of a one-device dynamic RAM cell with two exceptions. First, note that for a given ratio between the storage cap and the bitline cap (transfer ratio), the differential voltage on the bitlines will be about twice as large, because the cell in effect supplies a known reference voltage. In other words, a dummy cell to supply a half signal need not be used on the bitline not discharged (or charged for case 2) by the cell. Secondly, the state of t...