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On Chip Multiplex Testing Using Existing Latches

IP.com Disclosure Number: IPCOM000050573D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Bucelot, TJ: AUTHOR [+2]

Abstract

Latches normally present for other purposes on an integrated circuit chip are also useful for diagnostic testing by means of multiplexing hardware in technologies where adding multiplexers is advantageous with respect to adding latches.

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On Chip Multiplex Testing Using Existing Latches

Latches normally present for other purposes on an integrated circuit chip are also useful for diagnostic testing by means of multiplexing hardware in technologies where adding multiplexers is advantageous with respect to adding latches.

Each critical node not normally connected to a latch is equipped with an added fan-out to the input of an existing latch via a multiplexer input to the latch.

In diagnostic operation, the monitored node conditions are gated into the latches and read out for inspection according to a predetermined diagnostic sequence.

Because the parallel fan-out of many technologies is large and adds no significant delay, it is an advantageous trade-off to add multiplexers rather than latches to accomplish module testing. It is particularly advantageous in those technologies that use fewer devices to implement multiplexers than to implement latches.

In the figure, a group of latches 1, normally present for operational rather than diagnostic purposes, has for each latch a fan-in providing inputs from a number of operational circuits. An additional input via a multiplexer is added for diagnostic purposes.

A group of multiplexers 2 is connected to the group of latches respectively in accordance with diagnostic requirements, to connect respective critical nodes to their latch counterparts for diagnostic display or other diagnostic procedures.

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