Browse Prior Art Database

Simultaneous Decode of TM/BC(R) Pairs

IP.com Disclosure Number: IPCOM000050576D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Pomerene, JH: AUTHOR [+3]

Abstract

The high frequency of TM/BC(R) instructions suggests that simultaneous decode/execution can improve processor performance.

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Simultaneous Decode of TM/BC(R) Pairs

The high frequency of TM/BC(R) instructions suggests that simultaneous decode/execution can improve processor performance.

All references to instructions contained herein are to the IBM System/370 standard instruction set.

The major problem in simultaneous decode/execution of the TM/BC(R) or similar pairing is that a wide instruction register (IREG) is difficult to implement.

The use of a history table which maintains the (B, D) fields of the conditional branch (BC) and the R field of the BC(R) instruction, as well as the location of the pair, replaces the requirement to formally decode the branch.

The test under mask instruction is not indexable, and hence the TM/:BC requires no more than two general purpose register (GPR) reads. The dual- address generation process involved the normal handling of TM with the additional gating of the GPR required by the BC (R) to a second arithmetic logic unit (ALU).

The identification of the register and D field (as required) comes from the branch table.

As part of the process, the TM is validated and the next sequential instruction is compared to the relevant fields derived from the table so that the correct action has been validated. In the case of a taken conditional branch, the subsequent cycle may be available.

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