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Digital Receive Clock Recovery Circuit

IP.com Disclosure Number: IPCOM000050603D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 68K

Publishing Venue

IBM

Related People

Moore, BW: AUTHOR [+3]

Abstract

Fig. 1 shows a circuit useful for extracting a digital receive clock signal from a non-return to zero serial data stream. At high speed serial data rates, it is desirable to provide a receive clock signal with a minimum of up or down time of at least five times the oscillator clock frequency.

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Digital Receive Clock Recovery Circuit

Fig. 1 shows a circuit useful for extracting a digital receive clock signal from a non-return to zero serial data stream. At high speed serial data rates, it is desirable to provide a receive clock signal with a minimum of up or down time of at least five times the oscillator clock frequency.

Fig. 1 shows a circuit utilizing medium scale integration circuits to recover the digital receive clock from the serial digital data stream (:REC DATA). The receive data transition is detected by quad two input multiplexer 2, which may be a 74LS399 module, and is clocked by the oscillator signal's rising edge. A quad D-type flip-flop package 3, such as a 74LS175, connected in the manner shown in Fig. 1 with AND gate 4, provides the necessary hold and load signals to a synchronous four-bit counter 5, such as a 74LS163. Counter 5 generates a receive clock (:REC CLK) signal with the minimum high and low times of no less than 5 times the oscillator. This high and low time is required when using conventional SDLC (Synchronous Data Link Control) circuit modules operated at high data rates such as 1.0 Mbps or greater. A receive data delayed (:REC DATA DLYD) signal is provided as an output of flip-flops 3 and may be sampled by the positive edge of the receive clock output, as shown in the timing diagrams of Fig. 2. Note that no phase jitter should exist between the data delay and the receive clock rising edge.

For those applications not requiri...