Browse Prior Art Database

Improved Cycle Steal Service Sequence for IBM Series/1 Processor

IP.com Disclosure Number: IPCOM000050605D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 71K

Publishing Venue

IBM

Related People

Bhansali, MM: AUTHOR [+3]

Abstract

A mechanism is described for speeding up the cycle steal handshaking sequence for input/output (I/O) devices connected to an IBM Series/1 data processor. This increases the data transfer rate between the I/O devices and the Series/1 processor.

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Improved Cycle Steal Service Sequence for IBM Series/1 Processor

A mechanism is described for speeding up the cycle steal handshaking sequence for input/output (I/O) devices connected to an IBM Series/1 data processor. This increases the data transfer rate between the I/O devices and the Series/1 processor.

Fig. 1 shows some of the buses and signal lines which are contained in the processor channel bus which is used to connect one or more I/O devices to a Series/1 processor. Only those buses and lines are shown which are necessary for an understanding of the present improvement. In order to accomplish the high speed cycle steal service function, one new line is added to the Series/1 channel bus, namely, a high speed service gate return line. When the processor receives a service gate return signal on this high speed line, it then knows that it is to perform the high speed handshaking sequence, as opposed to the normal Series/1 handshaking sequence. Modified handshaking logic would be included in the Series/1 processor for accomplishing this purpose. For Purposes of providing compatability with existing Series/1 processors that do not have the high speed capability, the normal service gate return line is retained and a jumper arrangement is provided in the I/O device for selecting between the normal and high speed service gate return lines. For high speed operation, the jumper is placed so as to connect the output of the I/O device service gate logic to the high speed return line. This is the case shown in Fig. 1. For normal speed operation, the jumper would instead be placed to connect the output of the service gate logic to the normal return line. The remainder of this description will discuss only the high speed operation.

The key feature of the improved high speed service sequence operation is that there are no architected timing limitations required of the service sequence. Essentially, things are allowed to happen as fast as they can, and the speed of the service sequence is dependent only on the reaction time of the processor, its main storage unit and the I/O device. In this regard, the existing Series/1 data strobe signal is not used for the high speed service sequence.

Fig. 2 shows the timing of the high speed cycle steal service sequence used to transfer either a word or a byte of data from the I/O device into the processor main storage unit. It is assumed that a pol...