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Multilevel, Single Line Serial Priority Poll with Minimization of Pin Count and Propagation Delay

IP.com Disclosure Number: IPCOM000050606D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Kurtz, HL: AUTHOR [+2]

Abstract

A polling arrangement is described for use with a parallel bus, the arrangement having as its objective the reduction of pin requirements. Delays normally encountered are eliminated by providing direct through line connection of the Acknowledge Interrupt (ACKI) lines to each device and a more efficient arrangement of the "Poll-In" and "Poll-Out" pins. A delay circuit is provided to insure stabilization of the request state before enabling the propagation gate. A related article follows in this issue.

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Multilevel, Single Line Serial Priority Poll with Minimization of Pin Count and Propagation Delay

A polling arrangement is described for use with a parallel bus, the arrangement having as its objective the reduction of pin requirements. Delays normally encountered are eliminated by providing direct through line connection of the Acknowledge Interrupt (ACKI) lines to each device and a more efficient arrangement of the "Poll-In" and "Poll-Out" pins. A delay circuit is provided to insure stabilization of the request state before enabling the propagation gate. A related article follows in this issue.

Large numbers of pins are frequently required for attachments for processors, such as the IBM Series/1 Channel Translator. Such a device is required to handle four interrupt levels, i.e., a poll input and a poll output for each level, in addition to four direct-line acknowledge connections, making a total of 12 pins required for interrupt and acknowledgment and polling. Pin requirements are reduced in the scheme described here. Serial delays are also encountered. These are eliminated here by providing a direct-line connection of the ACKI lines to each device in conjunction with a separate ACKI polling connection for each level.

Fig. 1 is a block diagram showing the proposed method for reducing pin requirements. A direct connection is made of each ACKI line to each I/O port that is required to handle multiple interrupt levels. Of course, an I/O port, or functional unit, can be wired to a single fixed level, if so required. Regardless of the number of levels supported, a single psir of Poll-In (PI) and Poll-Out (PO) pins is provided for each functional unit or I/O port. The PI pin of the port physically nearest to the processor or bus controller is hardwired to an active level (Logic "1"). Each of the other PI pins is connected to the PO pin of the next higher priority port. Fig. 2 shows the poll propagation logic of a single port. It includes Request Flip-Flops "REQ PF 0" and "REQ FF 1". Other flip-flops may be provided as needed, indicated by dots 1. The logic also includes delay element 2 and other supporting circuitry. The conditions for propagating an active poll signal from PI to P0 are: 1. Any ACKI signal active, and

2. REQ FF co...