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Multilevel, Single Line, Serial Priority Poll Feature Poll In, Poll Out and Poll Capture

IP.com Disclosure Number: IPCOM000050607D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 5 page(s) / 69K

Publishing Venue

IBM

Related People

Kurtz, HL: AUTHOR [+3]

Abstract

This article represents an extension of a polling arrangement described in the preceding article. The primary feature of interest here is the arrangement of the "Poll-In", "Poll-Out" and "Poll-Capture" with an associated delay logic.

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Multilevel, Single Line, Serial Priority Poll Feature Poll In, Poll Out and Poll Capture

This article represents an extension of a polling arrangement described in the preceding article. The primary feature of interest here is the arrangement of the "Poll-In", "Poll-Out" and "Poll-Capture" with an associated delay logic.

The polling arrangement is applicable in systems having a central processing unit (CPU) and multiple input/output or special function subsidiary devices interconnected by a common bus. It may also be applicable in systems in which multiple processors share a common bus and attached resources, including memory and subsidiary devices. Two types of applications are possible. The first is in prioritization of interrupts where multiple devices can simultaneously and asynchronously request service from the CPU by presenting individual requests that interrupt normal program execution. The second is in direct memory access (DMA) operations where a processor or a device may present a request to a CPU or a separate bus controller or arbitrator to obtain temporary control of the bus for the purpose of transferring data to or from shared storage.

The following description is oriented primarily toward the interrupt prioritization application. There are two types of prioritization and arbitration: (1) Radial, with a separate request line and acknowledgment signal for each priority level, and (2) Serial polling to locate or identify the highest priority device of a number of devices presenting requests on the same line.

The features of interest are: (1) a single poll propagation path serving all request levels; (2) a single request-acknowledge line directly connected to each device, independently of which or how many request levels are served by the device; and (3) a single built-in delay element in each device acting in parallel with similar delay elements in each of the other I/O attachments on the same bus, to eliminate metastability effects commonly associated with serial polling.

In Fig. 1 are shown the external lines, between CPU or request arbitrator and I/O devices, used in the implementation of the multiple level priority polling scheme to be described. These lines consist of a number of acknowledge ID lines, which for interrupt requests may be part of the address bus, a request line for each priority level supported by the system, a single request acknowledge line common to all devices that have service request capability, and a single poll propagation daisy chain consisting of Poll-In (PI) and Poll-Out (PO) interconnections between devices. The PI pin of the highest priority device in the chain is connected directly to the Acknowledge (ACK) signal line from the CPU or request arbitrator. The PI pin of each lower priority device is connected to the PO pin of the next highest priority device such that an ACK signal applied to the PI pin of the first device will propagate to the lowest priority device unless it is interc...