Browse Prior Art Database

Microprocessor Interleave Instruction

IP.com Disclosure Number: IPCOM000050608D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 81K

Publishing Venue

IBM

Related People

Leininger, JC: AUTHOR

Abstract

A microprocessor designed to access several different types of semi-conductor memories with different speed characteristics may be configured so that the semiconductor memories used in a particular application are interleaved. This interleaving serves to reduce the effective access time of the memory. Magnetic core technology provided core memories that were designed with an "Advance" signal that indicated that data was being accessed and would be available a fixed time after advance. This allowed core memories to be interleaved, and when successive accesses were from the same memory, the processor would then halt until the "Advance" signal was received. Semiconductor memories do not have "Advance" signals, and require unique hardware controls to provide flexibility in the interleaving of memories.

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Microprocessor Interleave Instruction

A microprocessor designed to access several different types of semi- conductor memories with different speed characteristics may be configured so that the semiconductor memories used in a particular application are interleaved. This interleaving serves to reduce the effective access time of the memory. Magnetic core technology provided core memories that were designed with an "Advance" signal that indicated that data was being accessed and would be available a fixed time after advance. This allowed core memories to be interleaved, and when successive accesses were from the same memory, the processor would then halt until the "Advance" signal was received. Semiconductor memories do not have "Advance" signals, and require unique hardware controls to provide flexibility in the interleaving of memories.

Microprocessor addressing space may be shared by the microcode program as well as data. The microcode may be initially in RAM (random access memory), converted into ROM (read-only memory), while the data space must be in RAM.

When the access time of RAM and ROM are nearly equal, the cycle time of RAM is much greater than the access time. This restricts the memory cycle time at which the microprocessor can operate.

This invention provides a means to allow RAM interleaving for data and/or instructions but allows ROM to be either in the uninterleaved or interleaved state. It consists of an instruction, 'Set Interleave Mode', which can set the Interleave Instruction latch by use of an Instruction Interleave bit on the Instruction Memory Cycles and/or set the Interleave Data Latch on by the use of a Data Interleave bit for Data Memory Cycles. This allows for instructions to be partially in ROM and partially in RAM since the interleaving check can be turned on and off by the microprogrammer. A typical instruction is shown in Fig. 1. The overlap time field is programmable so t...