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Error Generator for Input Output Device Attachment

IP.com Disclosure Number: IPCOM000050609D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 4 page(s) / 86K

Publishing Venue

IBM

Related People

Crandall, DR: AUTHOR

Abstract

Hardware and software error handling capabilities are tested by real I/O attachment errors that normally happen at unpredictable times and that are often difficult or impossible to generate at will. An Error Generator is described that generates any error at will. This involves use of a special microcode "patch" in a diskette unit, like the IBM Model 4952 Model C unit which includes a Series/1 processor. Any error desired may be generated at any time so that error responses can be checked. The error generator patch program is loaded in advance of a debug session. The attachment will still work normally except that now an error may be generated at will, either from an attachment console stimulus or under system program control. This reduces hardware and software test time and effort.

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Error Generator for Input Output Device Attachment

Hardware and software error handling capabilities are tested by real I/O attachment errors that normally happen at unpredictable times and that are often difficult or impossible to generate at will. An Error Generator is described that generates any error at will. This involves use of a special microcode "patch" in a diskette unit, like the IBM Model 4952 Model C unit which includes a Series/1 processor. Any error desired may be generated at any time so that error responses can be checked. The error generator patch program is loaded in advance of a debug session. The attachment will still work normally except that now an error may be generated at will, either from an attachment console stimulus or under system program control. This reduces hardware and software test time and effort.

Errors are simulated by the microcode and the error results are returned to the processor in the various status codes. These include Cycle Steal Status and Condition Code. They also include RSB (Residual Status Block) and ISB/IIQ (Interrupt Status Byte/Interrupt Information Byte). If the Suppress Exception (SE) bit is on, soft errors will be retried by the I/O attachment. If these retries are successful in producing an error-free I/O operation, a permissive Device and Status is given at command end. On all I/O operations with the SE bit on that do not result in an unrecoverable error, an RSB is stored in the Series/1. Generally, the RSB contains soft error retry counters. The ISB is stored in the event of a hard error and contains status about the hard error, while the IIB is stored when no hard error is reported. The IIB contains the Permissive Device and Bit. These errors are produced by either a write device buffer command from the processor or Switch input from the Attachment Card console.

Typically, the error generator may be programmed to cause any one of twelve types of errors to occur during any one of thirteen types of commands. Further, to test soft error handling, the number of errors per command can be programmed.

Fig. 1 illustrates various inputs to the system. The following lists the types of errors to force and the types of commands to force the error on.

TYPE OF ERROR TO FORCE: 0 - NONE

1 - FORCE SEEK ERROR ON ANY CMD WITH IMPLIED SEEK

2 - ATTACHMENT DETECTED PARITY CHECK

3 - ATTACHMENT EQUIPMENT CHECK

4 - UNDERRUN/OVERRUN

5 - READ VERIFY ERROR

6 - CRC CHECK

7 - NO RECORD FOUND

8 - NO DATA FIELD FOUND

9 - STORAGE DATA CHECK

A - INVALID STORAGE ADDRESS CHECK

B -

C - USED BY CONSOLE ROUTINE

D -

1

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E - STORAGE PROTECTS CHECK

F - INTERFACE DATA CHECK.

TYPE OF COMMAND TO FORCE THE ERROR ON: 0 - FORMAT TRACK COMMAND

1 - VERIFY FORMAT TRACK COMMAND

2 - READ DATA COMMAND

3 - READ VERIFY - CRC CHECK COMMAND

4 - READ VERIFY - DATA COMPARE COMMAND

5 - READ SECTOR ID MAP COMMAND

6 - WRITE DATA COMMAND

7 - WRITE WITH VERIFY COMMAND

8 - READ DATA SPIRAL COMMAND

9 - READ VERIFY - CRC CHECK...