Browse Prior Art Database

Memory/Register Addressability Verification

IP.com Disclosure Number: IPCOM000050631D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Zufelt, IE: AUTHOR

Abstract

A memory-testing technique is described which can be implemented in hardware or software. A unique data pattern is written to each binary boundary within the address boundary range. This is accomplished by shifting a binary one through all the address bit positions.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 61% of the total text.

Page 1 of 2

Memory/Register Addressability Verification

A memory-testing technique is described which can be implemented in hardware or software. A unique data pattern is written to each binary boundary within the address boundary range. This is accomplished by shifting a binary one through all the address bit positions.

For each bit pattern written at an address, a series of read addresses are generated by ORing the write address and an intermediate address as explained below. The data at the read addresses are retrieved and compared to the written data. The read results will indicate whether an address line is stuck at one level or another.

The details of the algorithm are described for the case where only single bit failures are checked. In general, n-bit failures can be tested.

Let e(j,k) represent a binary vector of k bits, where k is the number of address bits in the system under test. All the bit values are zero except the j-th bit, which is a one. The write addresses (WAs) are then generated by e(j,k) for j = 0,1,2,. .
.,k-1. (The bit positions are considered to be zero-indexed.)

For each WA = e(j,k), a unique memory word (UMM) is written at the location addressed by WA. The memory word at WA = e(k)', i.e., a vector of k zeros, is read and compared to the UMW. If the comparison produces an equal result, then the j-th address line is determined to be stuck at a zero value.

Next, a series of intermediate addresses are generated according to IA = e(m,k), m = 0,1,2,. . ....