Browse Prior Art Database

Noise Cancelling Scheme in a Memory Array

IP.com Disclosure Number: IPCOM000050643D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Pricer, WD: AUTHOR

Abstract

A technique is provided for cancelling a noise source in a dynamic memory array having multiplexed sense amplifiers.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

Noise Cancelling Scheme in a Memory Array

A technique is provided for cancelling a noise source in a dynamic memory array having multiplexed sense amplifiers.

Dense arrays, such as those described in U.S. Patent 4,080,590, advantageously use multiplexed sense amplifiers. As shown in Fig. 1, a sense amplifier 10 is connected to a first pair of bit line segments B1L and B1R through first and second coupler/decoupler devices A1 and A2, respectively, and to a second psir of bit line segments B2L and B2R through third and fourth coupler/decoupler devices B1 and B2, respectively. A memory cell CA on bit line segment B1L and a memory cell CC on bit line segment B2L are coupled to a word line WLL, and a memory cell CB on bit line segment B1R and a memory cell CD on bit line segment B2R are coupled to a word line WLR in a known manner. Sense amplifier 10 is sequentially connected to the first pair of bit line segments B1L and B1R by turning on devices A1 and A2 and then to the second pair of bit line segments B2L and B2R by turning on devices B1 and B2.

A noise source unique to this multiplexed operation occurs from the coupling of the amplified information from the first pair of bit line segments B1L and B1R into the second pair of bit line segments B2L and B2R before the signal on the second pair of bit line segments B2L and B2R is amplified. The coupling per bit is relatively weak because each bit line segment is close to a substrate and comparatively far from the next bit line segment; however, in view of the long length of the bit line segments, the total coupling is substantial.

In order to cancel this noise, a first clock inverter 12 is attached to the end of bit line segment B1R and a second clock inverter 14 is attached to the end of the bit line segment B1L, as shown in Fig. 1.

In operation, if word line WLL is selected along with cell CA on bit line segment B1L, first clock inverter 12 is activated in this cycle. After the data in cell CA has been detected in amplifier 10, e.g., with the use of a dummy cell (not shown) on bit line segment B1R, a B1 pulse is applied to the control electrode of transistor T1 of inv...