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Error Correction Circuit and Algorithm for a Control Storage

IP.com Disclosure Number: IPCOM000050650D
Original Publication Date: 1982-Nov-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Howe, LD: AUTHOR

Abstract

This is a description of a technique to correct failures in a Control Storage (CS) with minimum or no correction delay. A mechanism such as ECC (Error Correction Code) could be applied to CS, but would slow its performance significantly. This error correction mechanism employs a correction flag and exclusive OR (XOR) circuitry. Only four bits are shown for illustrative purposes. This article also assumes that the CS is structured with a system which has the following: 1. CS bus with parity or similar check. 2. System retry mechanism capable of retrying soft errors. 3. Retry capable of re-writing the CS.

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Error Correction Circuit and Algorithm for a Control Storage

This is a description of a technique to correct failures in a Control Storage (CS) with minimum or no correction delay. A mechanism such as ECC (Error Correction Code) could be applied to CS, but would slow its performance significantly. This error correction mechanism employs a correction flag and exclusive OR (XOR) circuitry.

Only four bits are shown for illustrative purposes. This article also assumes that the CS is structured with a system which has the following: 1. CS bus with parity or similar check.

2. System retry mechanism capable of retrying soft errors.

3. Retry capable of re-writing the CS.

As shown in Fig. 1, the control storage array (CS) is provided with a extra array bit for each address to act as a correction tag. The output of the correction flag bit position is supplied to one input of a plurality of exclusive OR circuits XOR 0 through XOR 3, the other inputs of these gates being connected to the storage positions B through 3 as shown.

The outputs of the exclusive OR are connected to the inputs of associated latches LO through L3, respectively. The outputs of these latches constitute the latched control storage output bus.

A parity check circuit 5 has its inputs connected to the outputs of the latches and provides a machine check output. In operation,

1. The CS is assumed to be loaded with an original bit

pattern with no errors, as shown in column 2, Fig. 2.

2. Next, an error occurs...