Browse Prior Art Database

Polynomial Tester

IP.com Disclosure Number: IPCOM000050660D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Henn, HH: AUTHOR [+2]

Abstract

This tester improves known signature testing methods in that it is capable of detecting masked errors.

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Polynomial Tester

This tester improves known signature testing methods in that it is capable of detecting masked errors.

The figure shows an implementation of a polynomial tester for a complex logic circuit with, for example, 20 inputs and 20 outputs.

The inputs of the circuit under test (CUT) are stimulated by a stimulation register (STR) which can be a counter or any other random pattern generator. In the figure, STR is a Galois field counter with the generator polynomial g(x) = 1 + x/3/ + x/20/.

The figure shows the feedback connections necessary for implementing this polynomial with a cyclic shift register. Control signals A=1 and B = 0 are applied. At the beginning of the test, all shift register latches STR0 to STR20 are set to 1.

The outputs of CUT are connected to the inputs of a check register (CR) implemented similarly to STR. At the beginning of the test, all latches CR0 to CR20 of CR are set to 1. When a shift pulse is applied to the latches of CR, the outputs of CUT are modulo-2 added to the feedback bits and the contents of CR0 to CR19 by the XOR gates shown in the figure. Thus, the new state of CR is a function of its old state, the state of the outputs of CUT, and the feedback defined by g(x).

After the check register has changed its state, a shift pulse is applied to the latches of STR, and the procedure of alternately applying shift pulses to CR and STR proceeds until after 2/20/-1 steps ill possible input patterns, except for the all-zero pattern, have been generated> If CUT is faulty, the final pattern in CR will in all probability not be equal to the expected one.

However, single or multiple physical defects in logic circuits map cause highly correlated error patterns it the outputs. A defect which inverts bit n of CUT at time i and bit n + 1 at time i + 1 is undetectable, regardless of the length and feedback of CR. Also undetectable are errors which occur only if all inputs to CUT are zero, because the all zero pattern is not generated by STR.

In order to detect these errors, the input patterns must be applied in a sequence different from the fir...