Browse Prior Art Database

Receiver Circuit with a Zero Power Dissipation in a Steady State

IP.com Disclosure Number: IPCOM000050689D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 24K

Publishing Venue

IBM

Related People

Bansal, JP: AUTHOR

Abstract

A CMOS receiver circuit is disclosed which has zero power dissipation in a steady state. This circuit, which is shown in the figure, has a common gate input to the P channel FET device P1 and the two N channel FET devices N1 and N2.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 80% of the total text.

Page 1 of 2

Receiver Circuit with a Zero Power Dissipation in a Steady State

A CMOS receiver circuit is disclosed which has zero power dissipation in a steady state. This circuit, which is shown in the figure, has a common gate input to the P channel FET device P1 and the two N channel FET devices N1 and N2.

The common output node between P1 and N1 is connected as the output node of the circuit and also serves as the gate input to a third N channel FET device N3. The drain of the FET device N3 is connected to the drain potential V(DD) and its source is connected to the common node between the N channel FET devices N1 and N2.

When the input to the circuit is at a high potential, the N channel FET devices N1 and N2 conduct, whereas the P channel FET device P1 is off and the N channel FET device N3 is off. Therefore, the output of the circuit is at ground potential or a binary zero. In this state no current flows from the drain potential V(DD) to ground in the circuit.

When the input signal to the circuit is at a relatively low potential, the P channel FET device P1 and the N channel FET device N3 are conductive, whereas the N channel FET devices N1 and N2 are off. Thus, no current flows from the drain potential V(DD) to ground in the circuit. In this state, the circuit provides a positive output level.

This circuit has a number of advantages. It does hot dissipate significant power in the steady state whether its input is up or down. In addition, the channel width and hence th...