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Universal Test Engine

IP.com Disclosure Number: IPCOM000050693D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

McGovern, W: AUTHOR

Abstract

A test pattern preloaded in the programmable read-only memories (PROMs) 10 to 14 will excite the device under test (DUT) 16 to perform some function.

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Universal Test Engine

A test pattern preloaded in the programmable read-only memories (PROMs) 10 to 14 will excite the device under test (DUT) 16 to perform some function.

The PROMs in parallel provide any number of data and control lines to the device. These PROMs are controlled by direct memory access (DMA) control 18 which receives a programmed request, including a starting address and length of a test pattern, from processor 20. After receiving such a programmed request to start, the DMA 18 takes over, goes to the starting address, and presents sequential addresses to the PROM until a timer 22 runs out or a counter counts out. Then the DMA 18 stops functioning, and control is transferred back to the program in the processor 20.

Each PROM is accessed at the same address by the DMA 18. PROM 10 contains the initializing program starting at location 0000. As shown in Fig. 2, when the initial program PROM 10 is executing, PROMs 12 and 14 are inactive because their control patterns are preset to a reset or null function. When address 0050 is reached, the program initialization ends and the transfer of test patterns preloaded into all PROMs 10 to 14 begins.

A manual switch 26 and a 1 to 3-second timer 24 allow the engine, all associate apparatus and the device under test 16 to be reset manually for each 1 to 3-second period.

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