Browse Prior Art Database

Substrate Wiring Pattern for Partial Good Integrated Circuit Chips

IP.com Disclosure Number: IPCOM000050698D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Bartley, GK: AUTHOR [+2]

Abstract

Integrated-circuit (IC) chips having redundant bits are connected to substrate pads by a wiring pattern such that any bad bit may be isolated by a simple trace-cutting operation during packaging.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Substrate Wiring Pattern for Partial Good Integrated Circuit Chips

Integrated-circuit (IC) chips having redundant bits are connected to substrate pads by a wiring pattern such that any bad bit may be isolated by a simple trace- cutting operation during packaging.

Chip 10 in the drawing represents a memory array having five data bits B0- B4, any one of which may be defective. That is, chip 10 is actually used as a four bit wide memory, with one spare bit. Wiring pattern 11 on substrate 12 connects these bits to four substrate connection pads P0-P3, which in turn connect to output pins or other circuits (not shown). A bad bit is isolated with a conventional laser deletion tool by cutting various ones of the traces 20-27. For example, a bad bit at B1 in chip 10 is isolated by cutting traces 21, 22, 24 and 26, as indicated by the "X" marks in the drawing. This establishes the bit to pad connections B0-P0, B2-P1, B3-P2 and B4-P3, with B1 left unconnected. This simple wiring pattern can delete any of n bad bits without requiring a different substrate wiring pattern for each of several potentially defective bits. This technique may also be extended to other types of chips with redundant inputs or outputs.

1

Page 2 of 2

2

[This page contains 1 picture or other non-text object]