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Bootstrap Voltage Generator for Dynamic RAM Array

IP.com Disclosure Number: IPCOM000050700D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Aipperspach, AG: AUTHOR [+2]

Abstract

Circuit 10 (Pig. 1) drives heavy capacitive loads, such as the word lines of a dynamic random-access memory (RAM), above the 5-volt Vdd supply so that the full Vdd voltage can be written into the storage capacitors of the RAM cells.

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Bootstrap Voltage Generator for Dynamic RAM Array

Circuit 10 (Pig. 1) drives heavy capacitive loads, such as the word lines of a dynamic random-access memory (RAM), above the 5-volt Vdd supply so that the full Vdd voltage can be written into the storage capacitors of the RAM cells.

True and complement clock inputs 11, 12 drive output node 13 as shown in Fig. 2. When inputs 11 and 12 go high and low respectively, circuit node 1 is charged by field-effect transistor T35; output node 13 begins an upward transition via T36. Input 11 also pulls node k to ground via T39, which is clocked on by T22.

After a short delay produced by T1-T9, node b falls and cuts off T35, thereby isolating node 1. A falling voltage at node b then turns on T8, pulling node c to ground. T31 and T32 bootstrap node 1, enabling T36 to drive output 13 to Vdd. In addition, these events precharge capacitor C2 to Vdd.

Output 13 now charges node d high via T10. After a delay determined by T13-T16, node f falls and node e discharges via T14 and T15. T18 turns off, enabling T17 to charge node g high.

The voltage risc at node g turns on T21, T24, T33 and T34. T34 discharges node 1 and cuts off T36, allowing output 13 to float, so that it can be bootstrapped above Vdd. T33 prevents node m from being pulled below ground via C1 when node 1 is discharged to ground. T24 pulls node h to ground and turns off T39. Also, node i falls when g rises via T21; node j then rises because of T29. The push-pull action of...