Browse Prior Art Database

Oxide Wall Isolation for FET Integrated Circuits

IP.com Disclosure Number: IPCOM000050753D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Hu, GJ: AUTHOR [+2]

Abstract

This article presents a proposal for a simple and effective isolation structure for FET (field-effect transistor) integrated circuits. This isolation structure is particularly attractive for CMOS (complementary metal oxide Semiconductor). As shom in Fig. 1, The isolation between the n and the p channel devices consists of an oxide wall and a heavily doped region down below. When the doping concentration of this heavily doped region is sufficiently high (over 1 x 10/19/ cm/-3/), the minority carrier life time becomes so short that the parasitic bipolar latch-up problem can be significantly reduced.

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Oxide Wall Isolation for FET Integrated Circuits

This article presents a proposal for a simple and effective isolation structure for FET (field-effect transistor) integrated circuits. This isolation structure is particularly attractive for CMOS (complementary metal oxide Semiconductor). As shom in Fig. 1, The isolation between the n and the p channel devices consists of an oxide wall and a heavily doped region down below. When the doping concentration of this heavily doped region is sufficiently high (over 1 x 10/19/ cm/-3/), the minority carrier life time becomes so short that the parasitic bipolar latch-up problem can be significantly reduced.

The method of implementing this structure will now be described with reference to Fig. 2 through Fig. 6. In Fig. 2, a heavily doped n-type substrate is used as a starting material. After a layer of oxide is put over the substrate (this oxide may be thermally grown or deposited or a combination of both), a thin nucleating layer of polysilicon has to be deposited (1,2). One mask is needed to define the regions for all the active devices. The oxide in such regions is etched away by RIE (reactive ion etching) (CF(4) + H(2)). The RIE results in a vertical oxide profile, as shown in Fig. 3. Then a silicon growing process (2) is performed. Owing to the difference in the growth rate between the epitaxial layer over the single crystalline region and the polysilicon over the nucleating region, a flat surface can be acquired after a period of the growing process, as shown in Fig. 4. Fig. 5 shows the structure after an etch back process which can be well controlled by observing...