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Heavy Doping Isolation for CMOS Integrated Circuit

IP.com Disclosure Number: IPCOM000050754D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 66K

Publishing Venue

IBM

Related People

Chao, HH: AUTHOR [+3]

Abstract

This article relates generally to the fabrication of integrated circuits and more particularly to a method of providing heavy doping isolation for complementary metal-oxide semiconductor (CMOS) integrated circuits and the resulting device.

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Heavy Doping Isolation for CMOS Integrated Circuit

This article relates generally to the fabrication of integrated circuits and more particularly to a method of providing heavy doping isolation for complementary metal-oxide semiconductor (CMOS) integrated circuits and the resulting device.

Fig. 1 shows a cross-sectional view of a CMOS device 1 which can eliminate certain problems encountered in prior-art CMOS integrated circuits.

Because the minority carrier life-time in a heavily doped region is very short, n/+/ region 2 in device 1 significantly reduces the current gain of parasitic vertical pnp transistors normally formed by a p/+/ region 3, n-region 4 and p-region 5. Moreover, n/+/ region 2 forms a low resistive path to a power supply V(DD) (not shown), thus further retarding the interaction (the positive feed-back loop) between the vertical pnp and lateral npn transistor 6.

If the doping concentration in n/+/ region 2 is in the order of 10/19/ cm/-3/ and the thickness of that region is at about 1 Mum, the parasitic latch-up can be completely eliminated.

In device 1, the well-bouncing problem (analogous to the substrate bouncing problem) can also be reduced since n region 2 allows n-well 4 to be firmly tied to the potential of the power supply. Semi-ROX regions 7 are used to form the isolation on the silicon surface. Other conventional surface isolation schemes, such as full-ROX or no-ROX, may also be used. The reason for using ROX is that dielectric isolation, such as a deep oxide structure, may suffer from a serious leakage problem along the silicon-dielectric surface. This is particularly true for FET technology in which a lightly doped silicon surface is required. If the doping type of each region in Fig. 1 is converted to an opposite conductivity type, device 1 is still valid.

Figs. 2 through 5 show a method of fabricating device 1 of Fig. 1. Buried n/+/ region 10 in Fig. 2 is created by first forming n/+/ region 10 by diffusion and then growing an epi layer 11 on top. An oxidation and drive-in step before the grow...