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Methods for Fabricating P/+/ and N/+/ Poly SI Gates in a Single Poly SI Layer for Mosfet Applications

IP.com Disclosure Number: IPCOM000050755D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 58K

Publishing Venue

IBM

Related People

Bassous, E: AUTHOR [+3]

Abstract

Dual-polarity polycrystalline silicon (poly-Si) gates which are useful in CMOS integrated circuits can be readily fabricated by novel simplified processes described in this publication.

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Methods for Fabricating P/+/ and N/+/ Poly SI Gates in a Single Poly SI Layer for Mosfet Applications

Dual-polarity polycrystalline silicon (poly-Si) gates which are useful in CMOS integrated circuits can be readily fabricated by novel simplified processes described in this publication.

The performance of high-density CMOS integrated circuits utilizing poly-Si gates is significantly enhanced by the use of p+ poly-Si and n+ poly-Si gates in the p-channel and n-channel devices, respectively. Compared to single-polarity gate structures, the fabrication of such dual-polarity devices requires an additional lithographic masking level which results in increased cost and processing complexity. Two alternative processes for fabricating dual-gate structures using the same number of lithographic masking levels as single- polarity gate devices with a minimal increase in processing complexity will be described.

The processes are restricted to the fabrication of the p+ and n+ poly-Si gates. The starting point, shown in Fig. 1A, represents a typical cross-section of a CMOS structure after ion implantation of the deep n-type well and p+ field, and growth of the recessed oxide. Figs. 1A, 1B, 1C and 1D illustrate the steps of Process I, which are as follows:
Step 1 (Fig. 1A) - Deposit poly-Si (approx. 300 nm). - Apply resist. - Define gates. - RIE 90% poly-Si. - Strip resist. (Alternatively, RIE 100 % poly-Si,

strip resist,

deposit approx. 30 nm poly-Si.)

Step 2 (Fig. lB) - Deposit borosilicate glass (BSG) + SiO(2) (e.g., BN, BBr , spin-on). - Apply resist. - Define source and drain (n-channel device). - Etch SiO(2) and BSG. - Ion implant As.

Step 3 (Fig. 1C) - Strip resist. POCl(3) doping

(d...