Browse Prior Art Database

Methods for Making Symmetrical Transistor Structures

IP.com Disclosure Number: IPCOM000050756D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 4 page(s) / 48K

Publishing Venue

IBM

Related People

Reisman, A: AUTHOR [+4]

Abstract

This article relates generally to methods for fabricating semiconductor transistor devices and more particularly to methods for fabricating bipolar symmetrical transistor structures (STS).

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Methods for Making Symmetrical Transistor Structures

This article relates generally to methods for fabricating semiconductor transistor devices and more particularly to methods for fabricating bipolar symmetrical transistor structures (STS).

Two methods for fabricating symmetrical transistors, such as shown in Fig. 1, are disclosed in this article. In Fig. 1, an npn symmetrical transistor structure 1 is shown. An n/+/ emitter 2 has its surface flush with a top oxide layer 3 and is disposed within a p-type conductivity base region 4, a portion of which may be p/+/ polysilicon. A n collector region 5 is shown disposed in registry with emitter region 2 and between a pair of buried oxide regions 6. The structure of Fig. 1 may be fabricated by methods described hereinbelow in conjunction with Figs.
2.1-2.9 and Figs. 3.1-3.6.

Figs. 2.1-2.8 show the structure of Fig. 2.9 at intermediate stages in its fabrication. Fig. 2.1 shows a mesa-like structure 10 of silicon substrate 11 after regions 10, 11 have been isotropically etched using an oxide layer 12 and a nitride layer 13 as an etch mask. The etching step creates an overhang 4. After the oxide and nitride have been patterned in a known way, overhang 4 is produced using plasma or chemical etching well known to those skilled in the semiconductor fabrication arts.

The structure of Fig. 2.1 is oxidized to form oxide everywhere on the exposed surfaces of substrate 11 and region 10. A thin layer of nitride is formed over the oxide. Then, using reactive ion etching, the thin layers of oxide and -nitride are removed everywhere except under the overhang, leaving oxide layer 14 and nitride layer 15 on the sides of region 10, as shown in Fig. 2.2.

The structure of Fig. 2.2 is then thermally oxidized growing a recessed oxide 16 except where nitride layer 15 is present, producing the intermediate structure shown in Fig. 2.3. Oxide 16 may be formed using any conventional method.

Fig. 2.4 shows a structure wherein oxide region 14 and nitride region 15 on the sidewalls of region 10 have been etched away using conventional phosphoric acid or plasma etching techniques. Nitride region 13 is relatively thick so it remains after the etching step has been carried out.

In a succeeding step, as shown in Fig. 2.5 silicon is evaporated directionally normal to substrate 11 so that silicon is deposited everywhere except on the sidewalls of region 10. The silicon, which is polycrystalline in character, is used to provide a nucleation surface for a silicon growth step. Alternatively, at Fig. 2.4, polysilicon can be deposited in a blanket form over all surfaces. Subsequently, it can be planarized using the same technique shown in Fig. 2.7 to expose the nitride using RIE techniques. Etch stops of nitride or underlying ozide are intrinsic in the structure.

Fig. 2.6 shows the structure of the preceding figure after silicon has been grom heterogeneously on the nucleating silicon layer. The resulting growth may be either...