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High Speed General Purpose Register with Resistive Feedback and Bootstrapped Input Control Gates

IP.com Disclosure Number: IPCOM000050763D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 34K

Publishing Venue

IBM

Related People

Chao, HH: AUTHOR [+2]

Abstract

A general purpose static register with a higher performance than conventional registers is disclosed. This high performance circuit is a static flip-flop using a single resistive feedback to partially decouple the input inverter from the output stage for faster write operations. Additional input control gstes are bootstrapped to further enhance circuit operation and to facilitate the use of ordinary logic levels.

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High Speed General Purpose Register with Resistive Feedback and Bootstrapped Input Control Gates

A general purpose static register with a higher performance than conventional registers is disclosed. This high performance circuit is a static flip- flop using a single resistive feedback to partially decouple the input inverter from the output stage for faster write operations. Additional input control gstes are bootstrapped to further enhance circuit operation and to facilitate the use of ordinary logic levels.

Referring to the above drawing, this publication discloses the use of a resistive feedback 1 in a latch 2 to replace the commonly used directly connected feedback. With this resistive feedback 1, the write speed of such a latch 2 is found to be improved by a factor of two. A self boosting input circuit 6 is also implemented to solve the problem associated with the low power supply voltage for scaled down devices. For example, a logic circuit with one-micron dimension devices has a power supply of 2.5W.25 V. The control signal is only 2.25 V for logic high at the worst-case power supply. For a one-micron logic circuit which has a power supply of 2.5 V, the control signal is normally 2.25 V for logic high. In this case, the voltage drops across the input gates can substantially degrade the write speed. It is found that a self-boosting circuit in the control gates can enhance performance by a factor of three.

The resistive feedback 1 shown is used to partially decouple the input 1 from the output node 0. The push-pull driver after the latch 2 is used for buffering heavy load. In a pull-up situation, which is the critical delay of the latch, the input signal sees essentially only the gate oxide of device 3. The output node 0 is decoupled by the resistive feedback 1, in contrast to a conventional cross- coupled latch wherein a DC current has to be supplied to pull up the "low" node. Through computer simulation, the register delay...