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Mechanism to Detect Bursts/Gaps of Cache Miss Activity

IP.com Disclosure Number: IPCOM000050767D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Hoevel, LW: AUTHOR [+2]

Abstract

Several techniques for improving the performance of a machine by tailoring its cache mechanism to local deviations from the average buffer miss rate is described. For example, the number of bytes transferred per miss (linesize) can be shortened while the buffer miss rate is high and lengthened while the buffer miss rate is low. This permits the fastest possible adaptation of the cache to gross locality changes (high buffer miss rate) by eliminating trailing edge delays due to transfer mechanism busy and processor/transfer-mechanism interlocks, while maintaining large transfers during periods of low contention. All such schemes depend, however, on the ability to predict local variations in the buffer miss rate.

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Mechanism to Detect Bursts/Gaps of Cache Miss Activity

Several techniques for improving the performance of a machine by tailoring its cache mechanism to local deviations from the average buffer miss rate is described. For example, the number of bytes transferred per miss (linesize) can be shortened while the buffer miss rate is high and lengthened while the buffer miss rate is low. This permits the fastest possible adaptation of the cache to gross locality changes (high buffer miss rate) by eliminating trailing edge delays due to transfer mechanism busy and processor/transfer-mechanism interlocks, while maintaining large transfers during periods of low contention. All such schemes depend, however, on the ability to predict local variations in the buffer miss rate. It has been found that the time distribution of the buffer miss rate is bivariate for most IBM System/370 environments, alternating between 10-14% and near zero.

Inversion of the low-frequency portion of the Fourier Transform of the hit/miss sequence resulting from storage references clearly identifies alternating patterns of "bursts" and "gaps" of cache missed. Although all bursts and gaps are identified by this technique, it is not realistic to apply it in a real-time, predictive manner. The mechanism described below, however, obtains a 90 percent correlation with the Fourier technique for trace-tape samples of typical IMS, TSO, and scientific programming environments.

Basically, this mechanism consists of a counter that is decremented by one for each memory reference, and o...