Browse Prior Art Database

Instruction Architecture for Offline Mode

IP.com Disclosure Number: IPCOM000050790D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 8 page(s) / 93K

Publishing Venue

IBM

Related People

Heath, CA: AUTHOR [+4]

Abstract

In the system illustrated in Fig. 1, attachment microprocessor 10 can be operated in two distinct modes relative to host processor 11 and devices 12: an "inline" mode in which the microprocessor operates as a simple I/O controller for supervising transfers of data between the devices and host processor, and an "offline" mode in which the microprocessor independently processes data derived either from the devices or host.

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Instruction Architecture for Offline Mode

In the system illustrated in Fig. 1, attachment microprocessor 10 can be operated in two distinct modes relative to host processor 11 and devices 12: an "inline" mode in which the microprocessor operates as a simple I/O controller for supervising transfers of data between the devices and host processor, and an "offline" mode in which the microprocessor independently processes data derived either from the devices or host.

In the inline mode the microprocessor interprets primary command vectors contained in device control block information arrays (DCBs), and sets up "cycle steal" controls 13, described in U.S. Patent 4,246,637. The cycle steal controls then operate to transfer data of arbitrary length between a device and host storage in a "cycle stealing" mode asynchronous to operations of both the microprocessor and host central processing. In the offline mode the microprocessor interprets secondary commands contained in a "command list" array pre-loaded into microprocessor storage by prior interpretation of a special "LOAD DCB" primary command function, and initiated by a special "START DCB" primary command function. This article concerns the architectures of these special DCB functions and secondary commands.

As shown in Figs. 2A and 2B, each DCB consists of eight words, designated as words 0 through 7. Each word contains 16 bits, designated bits 0 through 15. Word 0 defines a single data transfer direction relative to host storage (except for bidirectional START DCBs as defined below), and contains chaining and timeout parameters. The chaining parameter (1 bit) indicates whether another DCB is to be fetched and interpreted at the conclusion of the microprocessor controller's operation for this DCB. The timeout parameter is used by the microprocessor to determine if the time taken for executing this DCB has exceeded a predetermined time limit, and enables the microprocessor to abort "out of limit" sequences.

DCB word 1 contains a type specifier bit for distinguishing the DCB type (inline or offline) and type dependent information which is interpreted by the microprocessor in logical association with the type bit. For inline type DCBs, this typs dependent information defines data transfer parameters and data format information relative to the device interface. For offline type DCBs, this type dependent information distinguishes between LOAD and START DCB functions, and defines device interface and aggregate length parameters relative to START DCB functions. An offline- i.e., command list interpretation- sequence initiated by a START DCB may involve plural data transfer operations and the aggregate length just referred to above applies to the aggregate amount of data transferred by such operations. Such data transfers may be directed to and from host storage and to and from devices; hence, the START DCBs are termed "bidirectional".

DCB words 2, 3, 6 and 7 contain additional type dependent...