Browse Prior Art Database

Wait State Generator

IP.com Disclosure Number: IPCOM000050791D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Bland, PM: AUTHOR [+2]

Abstract

When utilizing an Intel 8086 microprocessor, it is desirable to have more flexibility in inserting additional wait states than that afforded by the conventional 8284 clock generator generally used in conjunction with the 8086 microprocessor. The circuit shown in Fig. 1 affords this flexibility in that only a single wait state is inserted into each CPU bus cycle that addresses memory or input output (I/O) devices which exist on the base planar board and, in addition, allows the utilization of slow memory and I/O circuits off the base planar board which require more than one wait state to be inserted.

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Wait State Generator

When utilizing an Intel 8086 microprocessor, it is desirable to have more flexibility in inserting additional wait states than that afforded by the conventional 8284 clock generator generally used in conjunction with the 8086 microprocessor. The circuit shown in Fig. 1 affords this flexibility in that only a single wait state is inserted into each CPU bus cycle that addresses memory or input output (I/O) devices which exist on the base planar board and, in addition, allows the utilization of slow memory and I/O circuits off the base planar board which require more than one wait state to be inserted.

Referring to Fig. 1, an 8284A clock generator is connected in the conventional fashion to an 8086 microprocessor and applies the Reset, Clock and Ready signals thereto. The Ready signal is applied from an AND-OR combination gate within the clock generator circuit. Connected to the AND-OR combination gate are a pair of ready signals RDY1 and RDY2 and a pair of address enable signals AEN1 and AEN2.

The AEN1 signal is connected to the Base RAM Signal from the random- access memory on the planar board. The RDY1 signal is connected to the Q output of a latch 10 which has the processor grant (PG) storage signal applied to the D input and the system clock signal applied to the CLK input.

The AEN2 signal is applied from the Q output of latch 12 which is clocked by the system clock signal, preset by the storage cycle complete (DRDY) signal and cleared by the Address Latch signal. The D input to latch 12 is connected from the Q output of latch 14 which also is clocked by the system clock signal and cleared by the Address Latch signal. The D input to latch 14 is coupled to the system address enable signal.

The RDY2 signal is applied to the AND-OR gate in the clock generator from the Q output of...