Browse Prior Art Database

Recessed Oxide Isolation with Offset Field Doping

IP.com Disclosure Number: IPCOM000050802D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Bakeman, PE: AUTHOR [+3]

Abstract

This semiconductor processing technique uses a single masking step to define both a thermally grown thick field oxide for semiconductor isolation and an offset self-aligned highly doped channel stopper by the use of a photomask which is initially patterned to define the channel stopper areas. The mask is then reduced in area by an etching technique to define the recessed oxide areas.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

Recessed Oxide Isolation with Offset Field Doping

This semiconductor processing technique uses a single masking step to define both a thermally grown thick field oxide for semiconductor isolation and an offset self-aligned highly doped channel stopper by the use of a photomask which is initially patterned to define the channel stopper areas. The mask is then reduced in area by an etching technique to define the recessed oxide areas.

Current MOSFET processing technologies use high level doping under thick oxide field regions in order to prevent parasitic leakage in these areas. Known techniques include a self-aligned process in which the field oxide mask is also used to define the doping area. This technique produces an overlap between the field doping and FET channel edges and/or diffusion regions, causing narrow channel effects and increased diffusion perimeter capacitance. Another technique uses two masks and provides an offset between the highly doped channel stopper regions and the edges of the field oxide. This technique suffers from inherent mask alignment tolerances which must be allowed for in device design.

In this technique, silicon nitride masked field oxidation is used as shown in Fig. 1, which includes a semiconductor substrate 10 having a thin silicon dioxide layer 12 and a silicon nitride layer 14. A photoresist masking layer 16 is provided and is patterned to define areas in which the offset ion-implanted field areas are to be provided. For a p-type substrate, p-type ions are ion-implanted through layers 14 and 12, as shown by arrows 18, to provide a high concentration layer 20 of p-type impurity. Following the implant of the field regions, t...