Browse Prior Art Database

Boundary Crossing Within a Cache Line

IP.com Disclosure Number: IPCOM000050824D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 52K

Publishing Venue

IBM

Related People

Ngai, AY: AUTHOR [+2]

Abstract

When a CPU does a multiple byte storage access, the data can spread across the data bus width boundary. If the CPU-storage data bus is 8 bytes wide and the requested data is within an 8-byte boundary, the storage access is done in one machine cycle. If the requested data is across the 8-byte boundary, two machine cycles are usually needed to complete the access.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

Boundary Crossing Within a Cache Line

When a CPU does a multiple byte storage access, the data can spread across the data bus width boundary. If the CPU-storage data bus is 8 bytes wide and the requested data is within an 8-byte boundary, the storage access is done in one machine cycle. If the requested data is across the 8-byte boundary, two machine cycles are usually needed to complete the access.

If the cache is designed as shown in Fig. 1, most of the cross-boundary operation can be done in one machine cycle. The cache is divided into segment A and segment B.

Segment A contains all even doublewords, and segment B contains all odd doublewords, as shown in Fig. 2. Each segment provides 8 bytes of data, and each segment has a set of data registers. The requested data is merged from the data registers by the byte flags to the CPU via a byte shifter for data alignment.

In a three-byte addressing scheme, the lower-order cache address bit corresponds to address bit 20, as shown in Fig. 3. This address points to the beginning location of the requested data. If the requested data begins in an even doubleword and ends in an odd doubleword, then the same address is used to access the two segments at the same time. Both doublewords are also latched in the data registers. If the requested data begins in an odd doubleword and ends in an even doubleword, then the addresses of the two segments are different. The address of the requested data is used to access segment B. This address also feeds an incrementer 5. The output of the incrementer is used to access segment A. In this way, both doublewords are accessed at the same time.

Since a cache page is usually 64 bytes or 128 byte,s the address incrementer is across two or three address bits. The incremeter can be implemented by adding one more stages of circuit delay to the address assembler path prior to the address register.

The address together with the length of the requested data determines the cross-boundary condition and...