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High Speed Signed Binary Multiplication

IP.com Disclosure Number: IPCOM000050827D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 58K

Publishing Venue

IBM

Related People

Gooding, DN: AUTHOR [+3]

Abstract

This article describes a method to perform high speed multiplication on signed binary fixed point numbers. For purposes of illustration, the signed binary number will be defined as being 32 bits in length (bits 0-31), with the most significant bit (bit 0) being the sign. If the sign bit is equal to 0, the number is positive. If the sign bit is equal to 1, the number is negative.

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High Speed Signed Binary Multiplication

This article describes a method to perform high speed multiplication on signed binary fixed point numbers. For purposes of illustration, the signed binary number will be defined as being 32 bits in length (bits 0-31), with the most significant bit (bit 0) being the sign. If the sign bit is equal to 0, the number is positive. If the sign bit is equal to 1, the number is negative.

In forming a negative number, the positive representation of the number is taken and put into twos complement form. The twos complement of a number is formed by inverting all the bits in the number and then adding 1 to the low-order position.

Fig. 1 shows a configuration of a high speed multiplier. This multiplier is designed for floating point multiplication of two 56-bit floating point fractions. Since floating point fractions are always in absolute value form, negative operands are never encountered, and the product is always a positive binary number. The present arrangement modifies this multiplier design so that it can operate with floating point or signed binary fixed point numbers. We will first discuss the floating point multiplication, then follow with a discussion of the modification and operation of signed binary fixed point multiplication.

In operation, two operand registers are used. They are X and Y, and are 56 bits in length, the length of the floating point fraction. Areas A, B, C and D (Fig. 1) represent four 28 x 28 bit array multipliers. The array multipliers multiply two 28-bit numbers and produce a partial product in final sum form. To multiply X - Y, four partial products are formed. Thus:

X . Y=(X(H) . Y(H)) + (X(L) . Y(H)) + (X(H) . Y(L)) +

(X(L) . Y(L)) where X=X(H) + X(L) and Y=Y(H) + Y(L).

These partial products are subsequently aligned as shown in Fig. 1 and added in a carry-save adder tree followed by a full adder to produce the final product.

In operation, the operand registers are divided into four 28-bit sections, i.e., X(H), X(L), Y(H), Y(L). These are the 28-bit inputs which drive the array multipliers to produce the partial products. For example, the "A" wedge shown is the output of array "A" which is driven by X(H) and Y(H). Array "B" is driven by X(L) and Y(H).

The product (X . Y) is 112 bits in length (0-111), where bit 0 is the most significant bit and 111 the least significant.

The modification to this multiplier to multiply signed binary 32-bit numbers consists of four items. They are: 1. Aligning and adjusting the operands and their placement

in the X and Y registers.

2. Extending the operands and performing additional

multiplication on the extensions.

1

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3. Adjusting the f...