Browse Prior Art Database

Programmed Cycle Steal for Microprocessor Based PIO Bus

IP.com Disclosure Number: IPCOM000050828D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Callahan, RW: AUTHOR [+4]

Abstract

This arrangement offers a technique to maximize the programmed cycle steal speed, for a microprocessor-based on PIO interface, by reconfiguring the CSCB (cycle steal control byte) with a minimal external hardware and taking advantage of the processor's user interrupt architecture and post increment address modes. At the same time, no stringent timing requirements are needed between the PIO interface and the device adapters, since the data transfer operation takes place with strict hand shaking.

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Programmed Cycle Steal for Microprocessor Based PIO Bus

This arrangement offers a technique to maximize the programmed cycle steal speed, for a microprocessor-based on PIO interface, by reconfiguring the CSCB (cycle steal control byte) with a minimal external hardware and taking advantage of the processor's user interrupt architecture and post increment address modes. At the same time, no stringent timing requirements are needed between the PIO interface and the device adapters, since the data transfer operation takes place with strict hand shaking.

The adapter presents the CSCB information to the PIO interface during CSG (cycle steal grant) time. The CSCB contains control information that is needed in the performance of the operation. A typical CSCB incorporated in the UC-PIO (Universal Controller-Prograammd Input//utput Bus) is as shown in Fig. 1A. The microprocessor PIO interface modifies this CSCB as shown in Fig. 1B and presents to the microprocessor an 8-bit vector number during "INTERRUPT ACKNOWLEDGE" time. The processor translates the vector number into a full 24-bit address by multiplying the vector by 4, and branches to that address to service the interrupt. An address register of thQ microprocessor is dedicated to store the data buffer address, which is set up prior to initiating the cycle steal request, using the associated CSCB. Another address register is dedicated for holding the memory-mapped PIO interface address. By doing so, the need for saving...