Browse Prior Art Database

Improved Instruction Fetch in a Pipeline Processor

IP.com Disclosure Number: IPCOM000050829D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Ozvold, JL: AUTHOR

Abstract

A processor that is designed to perform pipelined fetching of instructions loses its speed advantage when execution does not continue with the next sequential instruction. One example is when the processor is executing program loops. When the execution of the program returns to the beginning of the loop, the instructions that were fetched in the pipeline must be ignored.

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Improved Instruction Fetch in a Pipeline Processor

A processor that is designed to perform pipelined fetching of instructions loses its speed advantage when execution does not continue with the next sequential instruction. One example is when the processor is executing program loops. When the execution of the program returns to the beginning of the loop, the instructions that were fetched in the pipeline must be ignored.

As shown in Fig. 1, two special registers are provided in the processor. The first register, the "stored program counter register" 3, is loaded with the address of the instruction at label "loop." The second register, the "stored instruction register" 5, is loaded with the command at address "loop." An additional control bit called "stored instruction valid bit," stored at 7, is needed to determine if the address and command are valid.

Fig. 2 is a flow chart of the operation of the conditional branch instruction.

Fig. 3 is a program that will be used to demonstrate the principle.

When the processor executes the command at address X, assume the "stored instruction valid bit" is off, indicating the two registers do not contain a good value. The processor executes the command at address X 2 and continues on as normal. When it executes the conditional branch at address X + A, execution will continue with either X + C or return to address X + 2 "loop." If the execution should go to address X 2 "loop," then the address of "loop," X + 2, is stored in th...