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Repair by Reconfiguration Using Replicated Chips Intended for Checking

IP.com Disclosure Number: IPCOM000050831D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 5 page(s) / 56K

Publishing Venue

IBM

Related People

Agnew, PW: AUTHOR

Abstract

A recently announced microprocessor family provides for any chip to act either as a MASTER or as a CHECKER. In the intended use, the Primary Inputs (PIs) and Primary Outputs (POs) of two such chips are wired together. The chips perform identical processing on the logic signals they receive from the PI wires. The MASTER places the results of its processing onto the PO wires, which drive other chips in the system. The CHECKER treats the PO wires as more inputs. At each suitable clock time, it compares the signals it received from the MASTER on the PO wires against the results of its own processing. If this comparison shows any disagreement, then the CHECKER places a 1 on its CHECK output.

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Repair by Reconfiguration Using Replicated Chips Intended for Checking

A recently announced microprocessor family provides for any chip to act either as a MASTER or as a CHECKER. In the intended use, the Primary Inputs (PIs) and Primary Outputs (POs) of two such chips are wired together. The chips perform identical processing on the logic signals they receive from the PI wires. The MASTER places the results of its processing onto the PO wires, which drive other chips in the system. The CHECKER treats the PO wires as more inputs. At each suitable clock time, it compares the signals it received from the MASTER on the PO wires against the results of its own processing. If this comparison shows any disagreement, then the CHECKER places a 1 on its CHECK output.

The MASTER and CHECKER are identified by card wiring. The MODE input of the master chip is held at 1 by being wired to the supply voltage line. The MODE input to the CHECKER chip is held at 0 by being wired to ground. A system based on the announced microprocessor family can therefore check those chips by providing a redundant CHECKER for each functional chip. Such a system can respond to any CHECK output going to 1 by cancelling the operation in progress, restarting, and attempting to continue. This attempt is successful if the failure was intermittent. The system must stop and await manual repair if the failure was solid.

The same chips can be used to construct a self reconfiguring system capable of automatic repair. It is necessary to provide more than two copies of each chip. It is also necessary to provide a Support Processor to control each copy's MODE input, rather than wiring the MODE inputs to fixed voltages.

For simplicity of description, it will be assumed that a chip is a complete processor. Consider a system containing four processors and a Support Processor connected as shown in Fig. 1. Such a system can operate in the three modes (A) "checked and diagnosed", (B) "checked", and (C) "unchecked", as follows: A. CHECKED AND DIAGNOSED OPERATION Setup.

Any one processor is MASTER, with its MODE input equal to 1, and the remaining processors are CHECKERS, with their MODE inputs equal to 0. Operation.

All processors receive PIs in parallel, the one MASTER provides the POs, and the CHECKERs compare those POs to results that they compute from PIs. Operation continues until two or more CHECKERS give check outputs equal to 1. Then the MASTER is BAD and should be configured out. If only one CHECKER'S CHECK output equals 1, then the "single failure" assumption implies that one CHECKER has failed and the MASTER is GOOD. One of the processors may be known to be BAD, and be ignored, so checked and diagnosed operation applies when any three

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processors are good. If two of four processors, all presumed to be GOOD, give CHECK outputs equal to 1, then the tie should be resolved by assuming that the MASTER and one CHECKER are correct. This avoids unnecessary reconfiguratio...