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Fast Destructive Overlap Move Instruction Execution Algorithm

IP.com Disclosure Number: IPCOM000050833D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 4 page(s) / 40K

Publishing Venue

IBM

Related People

Ngai, AY: AUTHOR [+2]

Abstract

For certain instructions, the operands can overlap destructively within the width of the data bus. The operands overlap destructively if the first operand location is used as a source after data is moved into it. The conditions of operand overlap are: (1) If operand 1 > operand 2 0 < operand 1 - operand 2 < 8 where 8 is the width of the data bus, for example, in bytes (2) If operand 2 > operand 1 0 < operand 1 + twos complement of operand 2 < 8 Note: Operand 1, 2, are storage locations. When such a condition is detected, the system moves one byte at a time. The CPU fetches one byte of data from the second operand location and stores this data in the first operand location. Then both operand addresses are updated by one.

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Fast Destructive Overlap Move Instruction Execution Algorithm

For certain instructions, the operands can overlap destructively within the width of the data bus. The operands overlap destructively if the first operand location is used as a source after data is moved into it. The conditions of operand overlap are: (1) If operand 1 > operand 2 0 < operand 1 - operand 2 < 8 where 8 is the width of the data bus, for example, in bytes (2) If operand 2 > operand 1 0 < operand 1 + twos complement of operand 2 < 8

Note: Operand 1, 2, are storage locations.

When such a condition is detected, the system moves one byte at a time. The CPU fetches one byte of data from the second operand location and stores this data in the first operand location. Then both operand addresses are updated by one. The CPU continues the fetch and store operation for the number of bytes specified in the length field of the instruction.

The execution of a Move, Move Numerics and Move Zones instruction with destructive operand overlap is much faster with the algorithm shown in the flow diagram of Figs. 2A and 2B in addition to the parallel gating circuitry shown in Fig. 1. Usually, flags are used to gate a byte of data at the shifter input to any byte location at the shifter output. The condition for the parallel gating function is incorporated in flag generation, the parallel gating function being done in the shifter.

The shifter 1 is fed by the storage bus 3 or Register B and feeds the storage bus and Register A, as shown in Fig. 1.

Register B provides 8 bytes of data, for example, to the shifter. The source data is fetched from storage, right justified in the shifter, and latched in Registers A and B. The source data in Register B is rotated or parallel gated in the shifter by the flags. Up to 8 bytes of the shifter output are stored in the operand 1 location in each store operation. The shifter output is also latched in Register A. The operand 1 address and the length field are updated by the amount stored. The data in Register A becomes the source data for the next store operation, if needed. This cycle repeats for the entire instruction.

The two operand fields together with the length field determine the destructive operand overlap condition. The source data is at the second operand address. The number of bytes, N, in the source data is different between the first and second operand fields. The source data is fetched and right justified via the shifter. The shifter output is latched in Register A. Fig. 3 shows a portion of storage and the source data in Register A. It is sufficient to fetch the source data only once because the data is used repeatedly through the entire instruction.

The number of bytes from the operand 1 location to the doubleword boundary is indicated by "X" which is the twos complement of the low-order 3 bits of the operand 1 address. Fig. 3 shows that X is greater than N. The source data in Register A is set into Register B. The N bytes in Re...