Browse Prior Art Database

Data Base Control and Processing System

IP.com Disclosure Number: IPCOM000050835D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 4 page(s) / 81K

Publishing Venue

IBM

Related People

Marsh, ER: AUTHOR

Abstract

There is disclosed a Data Base Control (DBC) and Processing System (PS) comprising a host processor and a plurality of satellite processors having data interfaces connected to the main processor and main data storage by a data switch matrix.

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Data Base Control and Processing System

There is disclosed a Data Base Control (DBC) and Processing System (PS) comprising a host processor and a plurality of satellite processors having data interfaces connected to the main processor and main data storage by a data switch matrix.

Referring to Fig. 1 input/output, the system data base (DB) is implemented in conjunction with a system or host processor 1 and its associated channels running under a conventional operating system. This system incorporates a number of separate (I/O) processor (IOP) microcomputers 3 which will have their own storage and I/O buffer memory. The data I/O of each file control micro- computer will be directed to a data switch matrix 5 internal to the data base control and processing system. The switch can then provide 'N' I/O paths for data from the IOPs by connecting their buffer memory to the memory of another unit attached to the switch's external lines. The arrangement permits any of several disk controller IOPs to be dynamically connected 1 to 1 to any external line not already simultaneously set to another similar connection.

Transfers from the data base can also be made to the internal memory of the host system. The data base processor also receives and transmits control signals directly to the subsystem processors over control lines 7 through which requests for data and status are exchanged.

I/O command operations at the IOPs would be handled identically to known channel I/O sequences with the exception that information to be passed to the attached external processor bank will be read into the IOP's storage where it is buffered prior to transmission (or conversely for write, to the file) which could overlap its operation in terms of data transfer for read/write. Memory to Memory transfers could be made to or from the DBC and PS main storage as the end part of a standard I/O channel data transfer command for the use of the host system. Transfers could then be made between the IOP buffer and host main-storage to provide data base information to the host and its conventional processing operations. A second path, controlled by SIO/CCW (Start Input Output/ Channel Control Word) commands from the host (but independent of interference with the host's main memory paths), is provided to distribute required data to the attached peripheral processor complex. Transfers of data from/to external subsystems through the data switch would be controlled by the host, but the data transfer, which occurred as a result, would be only between the external subsystem(s) and the IOP buffer memory for the device in question. However, the I/O operation to fetch the data would look exactly like a standard SIO/CCW interpretation sequence to the host system except that no information would be transferred in or out of the host storage.

Requests for service are generated by peripheral subsystems and sent via a signaling protocol using known serial coaxial mechanisms. This signaling i...