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Browse Prior Art Database

Amplitude Detector with Improved Tracking and Memory Capability

IP.com Disclosure Number: IPCOM000050857D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Ward, ED: AUTHOR [+2]

Abstract

The described circuit tracks amplitude peaks and avoids the compromise of classical circuits utilizing time constants (T=RC) while providing tracking and retention of peak values in memory until updated.

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Amplitude Detector with Improved Tracking and Memory Capability

The described circuit tracks amplitude peaks and avoids the compromise of classical circuits utilizing time constants (T=RC) while providing tracking and retention of peak values in memory until updated.

Turning now to the drawing, an example of an amplitude detect and hold circuit 100 is illustrated therein. As shown, the circuit comprises two sample and hold stages, 101 and 102 (for example, Datel Corporation SHM-IC-1) with appropriate logic to control the tracking and necessary memory capability. The sample and hold circuits 101 and 102 are cascaded and under control of logic circuits 103 and 104, illustrated in dotted lines in the drawing. As the analog signal input from one of the lines 73-75 reaches its peak value, or amplitude value, the input and output of the first stage sample and hold 101 will be of equal value, and logic control 103 will switch rapidly from "sample" to "hold." However, when the analog signal decreases from the crest value, the analog comparator circuit 105 will instantly, because of the signal at the junction 106, set the first stage sample and hold 101 to the hold mode. As this hold condition appears at the first stage sample and hold 101, the converse signal (sample condition) appears at the second stage sample and hold 102 because of the logic inverter 107 and its output signal appears on line 107a. As the analog signal continues to change, a valley condition of the wa...