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Random Access Data Acquisition System

IP.com Disclosure Number: IPCOM000050872D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Anolick, ES: AUTHOR [+5]

Abstract

This system captures data from any of n test points in a system under test. It uses n 16-bit registers which are individually latched and addressed. Data is fed to the registers via a common 16-bit bus. The resolution of the system is determined by the rate at which the data on the bus is updated. Data must be held static on the bus except during updating.

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Random Access Data Acquisition System

This system captures data from any of n test points in a system under test. It uses n 16-bit registers which are individually latched and addressed. Data is fed to the registers via a common 16-bit bus. The resolution of the system is determined by the rate at which the data on the bus is updated. Data must be held static on the bus except during updating.

Each 16-bit register has a latch (enable) line which enables incoming data to be latched into the register. Data in each register is continuously updated until the latch line drops, disabling further inputs to the register.

The output of each register is a 16-bit word connected to a common bus. Since only one register may be addressed, via the output address line, at any given time, only one register's output may be on the bus at any given time.

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