Browse Prior Art Database

Enhanced Sensor Tracking

IP.com Disclosure Number: IPCOM000050877D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Stranko, TA: AUTHOR

Abstract

In hardware systems where a multitude of sense lines must be tracked dependent on the changing state of the environment, it is important that critical sense lines be responded to quickly when activated. A typical scheme for doing this would be to divide the sense lines into groups, compare the lines per group with mask bits to activate an interrupt, and funnel a single interrupt line per group to an intelligent controller. The scheme described here expands on this idea and improves its availability and reliability.

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Enhanced Sensor Tracking

In hardware systems where a multitude of sense lines must be tracked dependent on the changing state of the environment, it is important that critical sense lines be responded to quickly when activated. A typical scheme for doing this would be to divide the sense lines into groups, compare the lines per group with mask bits to activate an interrupt, and funnel a single interrupt line per group to an intelligent controller. The scheme described here expands on this idea and improves its availability and reliability.

The figure shows a hardware data flow. All of the external sense lines to be monitored are divided into N groups of 16 bits (2 bytes for each interface to an intelligent controller). At the heart of this mechanism is a free-running counter of 4 bits (or as many bits as are needed to allow sampling of the N groups). This counter runs with an output decoder selecting different sense groups each cycle. Simultaneous with selection of a sense group, the counter output bits are used to access an array whose width is equal to the group width plus bits for parity and check bits.

During each cycle, the appropriate sense group and mask bits are compared to see if a critical sense line activation should be reported. If an interrupt is indicated, a bit is set into the digital event register (DER) in accordance with the decoded counter selects, and a single interrupt line raised to the controller (or control logic).

Once the controller recognizes the interrupt line, it can read the data content of the DER to find the group interrupt and follow with a read to the group logic to find the particular sensor.

Two functions added to this mechanism improve its characteristics. First, two check bits are added at each array address. As each address is accessed, the data read out is parity checked for integrity. If it is out of parity, it is still used but the address is trapped in a register (not shown). This register can be read by the contr...