Browse Prior Art Database

Data Shifter

IP.com Disclosure Number: IPCOM000050927D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Kugel, LE: AUTHOR

Abstract

Successive multiplexer stages perform multiple-position left and right data shifting in a Josephson circuit computer.

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Data Shifter

Successive multiplexer stages perform multiple-position left and right data shifting in a Josephson circuit computer.

As shown in Fig. 1, the data shifter is defined by using successive multiplexer stages M1, M2, M3. The first stage M1 shifts the data 0, 1, 2, or 3 positions. The second stage M2 shifts the data 0, 4, 8, or 12 positions. The third stage M3 shifts the data 0, 16, 32, or 48 positions. Since the shifting is cumulative, a 25- position shift is accomplished by shifting stage 1, 1 position; stage 2, 8 positions; and stage 3, 16 positions.

As shown in Fig. 2, each bit of a multiplexer can be implemented with a 4- way AND circuit 10 by defining logical true=no current. Then the current injection logic (CIL) 4-way AND circuit logically becomes a 4-way OR circuit with ANDed inputs.

The table on the next page shows the output bit 0 of the multiplexer for different control line states. The multiplexer output is forced to "false" if all control lines are false. The multiplexer output is the four inputs ORed, if the control lines are all true. TABLE

T=True

F=False

0 1 2 3 Output

T F F F Input bit 0

F T F F Input bit 1

F F T F Input bit 2

F F F T Input bit 3

F F F F Logical False

T T T T Data Inputs ORed.

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