Browse Prior Art Database

Reduction of Punchthrough in Josephson Circuits

IP.com Disclosure Number: IPCOM000050929D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Anderson, CJ: AUTHOR [+2]

Abstract

In Josephson circuitry, punchthrough is a known phenomenon in which devices often do not reset when the supply waveform goes through zero. It is known that, if the dwell of the supply waveform around zero is increased, device resetting will occur. A circuit is described for increasing dwell in the power supply waveform in order to insure resetting of the Josephson logic circuits between logic cycles.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 90% of the total text.

Page 1 of 2

Reduction of Punchthrough in Josephson Circuits

In Josephson circuitry, punchthrough is a known phenomenon in which devices often do not reset when the supply waveform goes through zero. It is known that, if the dwell of the supply waveform around zero is increased, device resetting will occur. A circuit is described for increasing dwell in the power supply waveform in order to insure resetting of the Josephson logic circuits between logic cycles.

Fig. 1 shows a circuit for increasing dwell by introducing supply junctions J1, J2 in series with the supply resistor R(s) leading to the logic gate LC. During the regulated portion of the voltage waveform, the supply junctions are biased near the top of the current step at the gap in the non-linear resistance characteristic, but below the R(nn) region where noise might be a problem. As the voltage decreases during a polarity transition, the current to the logic gate initially drops rapidly but then dwells near zero because the supply junctions are now biased in the R(j) region.

An example of the waveforms obtained with this circuit is shown in Fig. 2, where the current waveforms L(LG) is plotted against time. This waveform has nearly twice the dwell as that provided by conventional supplies using a linear supply resistor.

In order to evaluate any dwell scheme, it is necessary to ask what it costs in current, power, and duty cycle. The present circuit will double the dwell for a reduction in duty cycle of only from 80 p...