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Software Realization of Hardware

IP.com Disclosure Number: IPCOM000050947D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 15K

Publishing Venue

IBM

Related People

Roth, JP: AUTHOR

Abstract

The disciplines of hardware software grew up in parallel, their interaction generally being restricted to interfaces. It is shown hers that they may be freely translated one into the other, usually with some loss of expressive efficiency.

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Software Realization of Hardware

The disciplines of hardware software grew up in parallel, their interaction generally being restricted to interfaces. It is shown hers that they may be freely translated one into the other, usually with some loss of expressive efficiency.

The form of the hardware is defined first. The form of definition is the so-called Regular Logic Design (RLD). Each circuit (logic block) is given an alphanumeric name; its function will be one of several logic primitives, which is assumed with no loss of generality to be always an AND-Invert (AI) of from 1 to k (e.g., k=4) inputs; the logic design is then defined by a list of circuit names, one line for each circuit in the logic design, followed by the equality sign followed by the function name, followed by the names of its inputs, separated by commas, all enclosed in parentheses, followed by a semicolon; if the graph of the design has feedback, then a pair of registers - memory devices - must be inserted in appropriately chosen feedback loops, gated at different clock times whose difference is of appropriate duration (to assure determinate operation of the hardware). In addition to circuits, a regular logical design has REGISTERS, which constitute memory elements. The symbol for this function will be REG. If y is the (binary) output of a register; if a and b are its data inputs, and c, the control, then write as part of an RLD containing this memory element y=REG(a,b,c).

Each feedback loop in the design will contain two such registers (gated at different clock times).

It is necessary to specify the primary outputs (POs) of an RLD and It is convenient to specify the primary inputs (PIs), although these may be computed from the RLD list. These are listed at the beginning of the RLD listing.

In addition to the RLD, there are, in general, MACROs, specifying well defined parts of the design. A MACRO is a well defined RLD; it is given its own unique alphanumeric name and is defined by its own RLD listing, the entries consisting of those for logic blocks or the names of its arguments and values. It is a convenient shorthand for a piece of regular logic, within a larger design. For the purposes of translation, assume that all macros have been expanded to their pure logical RLD format.

The first operation is to simplify the RLD. This is done here in two steps: first to reduce the logic to two-level form, treating the registers as sources of pseudo inputs and pseudo outputs, that is to say, represent a register as having both a pseudo input (memory input) and pseudo output (memory output). The P*-algorithm, described in (1), makes this transformation, in its DYNAMIC form (2).

Actually, in this form, the design is subdivided into several interconnected 2-level designs. Then, factorization on each 2-level cover is performed, further to economize the cost, with a controlled number of...