Browse Prior Art Database

Program Controlled Paging Scheme for Memory Expansion

IP.com Disclosure Number: IPCOM000050954D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Skelton, MH: AUTHOR

Abstract

A memory paging scheme is provided which utilizes program-controlled switching to select between memory modules that share the same address space to thereby expand the memory. With reference to the example shown in the figure, the address space has four sections designated C0, C1, C2 and C3. Sections C0 and C3 have unique memory. Sections C1 and C2 are each shared by two memory areas respectively designated by A and B and selected by the paging input to the chip select logic 10. For example, if an address is selected in area C1 and the paging line has been set to state A by the program, then memory C1A is accessed. However, if the paging line had been set to state B, then memory C1B would have been accessed.

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Program Controlled Paging Scheme for Memory Expansion

A memory paging scheme is provided which utilizes program-controlled switching to select between memory modules that share the same address space to thereby expand the memory. With reference to the example shown in the figure, the address space has four sections designated C0, C1, C2 and C3. Sections C0 and C3 have unique memory. Sections C1 and C2 are each shared by two memory areas respectively designated by A and B and selected by the paging input to the chip select logic 10. For example, if an address is selected in area C1 and the paging line has been set to state A by the program, then memory C1A is accessed. However, if the paging line had been set to state B, then memory C1B would have been accessed.

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