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Noise Resistant Peak Detector

IP.com Disclosure Number: IPCOM000050968D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 4 page(s) / 42K

Publishing Venue

IBM

Related People

Hense, KR: AUTHOR

Abstract

This article describes a peak detector for a magnetic recording channel which is insensitive to noise on either edge of the readback signals. As shown in Fig. 1, the peak detector comprises a threshold detector 10 and a slope detector 11 which are provided with the readback signal on input line 12. The output of the threshold detector 10 is connected to the set input of the flip-flop 14 which functionally controls single-pole, single-throw (SPST) switch S1. The output of the threshold detector 10 is also connected to one input of gate 15. The output of slope detector 11 is connected to the other input of gate 15. The output of gate 15 controls a single-pole, single-throw (SPST) switch S2.

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Noise Resistant Peak Detector

This article describes a peak detector for a magnetic recording channel which is insensitive to noise on either edge of the readback signals. As shown in Fig. 1, the peak detector comprises a threshold detector 10 and a slope detector 11 which are provided with the readback signal on input line 12. The output of the threshold detector 10 is connected to the set input of the flip-flop 14 which functionally controls single-pole, single-throw (SPST) switch S1. The output of the threshold detector 10 is also connected to one input of gate 15. The output of slope detector 11 is connected to the other input of gate 15. The output of gate 15 controls a single-pole, single-throw (SPST) switch S2.

The detector further includes a comparator 17 whose output is connected to a single-shot 18 and the reset input terminal R of flip-flop 14. Comparator 17 has one input 20 connected to a source of reference voltage and a second input terminal 21 connected to one plate of capacitor C1 which has the other plate also connected to the source of reference voltage.

Switch S2 functions to connect a current source 22 to the one plate of capacitor C1, while switch S1 functions to clamp the plate of capacitor C1 to a reset voltage source 23.

The operation of Fig. 1 is generally as follows. The threshold detector consists of a level detector which senses when the analog input signal 12 exceeds a predetermined level. The slope detector 11 is a differentiation circuit which determines the polarity of the slope of the input signal 12. The outputs of the threshold detector and slope detector are DC logic levels.

The flip-flop 14 operates switch S1 which clamps and unclamps capacitor C1. This capacitor C) is normally clamped to the positive reset voltage 23 during the reset state and is unclamped during the pulse detection sequence.

Logic gate 15 operates switch S2 to cause current source 22 to discharge the capacitor during a pulse detection sequence. A logic table showing the operation of the clamp and discharge current is as follows: 1 0 0 1 Unclamped 1 0 1 1 Unclamped 1 1 0 1 Unclamped 1 1 1 0 Unclamped 0 X X X Clamped
Note: Q is set when T goes from 0 to 1.

The voltage across the capacitor C1 is monitored by comparator 17. When the capacitor C1 is discharged to a voltage equal to V reference, comparator 17 switches and resets flip-flop 14. The comparator 17 also triggers single-shot 18 which produces an output pulse.

Fig. 2 shows the operation of the detector without noise present. The status of the peak detector prior to a pulse being received is as follows: 1. Threshold output T is negative.

1

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2. Slope S is undefined.

3. Flip-flop 14 is reset.

4. Capacitor C1 is clamped to V by S1 being closed.

5. I(disch) is on, but it does not discharge the capacitor

because the capacitor is clamped.

When an input pulse is received, the following sequence occurs:

1. The slope detector 11 output S becomes valid and is positive

as...