Browse Prior Art Database

Computer Bit Register Circuit

IP.com Disclosure Number: IPCOM000050979D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Moore, VS: AUTHOR [+2]

Abstract

The illustrated circuit is useful as a computer bit register or latch, and exhibits fast response and low power consumption characteristics. The portions below the dotted line in the drawing represent a presently conventional register circuit, and the portions above the dotted line represent load circuits which exhibit dynamic loading characteristics affecting the power consumption of the entire circuit structure.

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Computer Bit Register Circuit

The illustrated circuit is useful as a computer bit register or latch, and exhibits fast response and low power consumption characteristics. The portions below the dotted line in the drawing represent a presently conventional register circuit, and the portions above the dotted line represent load circuits which exhibit dynamic loading characteristics affecting the power consumption of the entire circuit structure.

Assume DATA IN is positive for entering a bit value of one into the indicated register/latch circuit, and that a positive transition is required at the "WRITE REG" input for gating each bit entry. Under these conditions, transistor TW1 will conduct, pulling node A to ground. This renders TM4 non-conducting, and since TW2 is non-conducting by virtue of the DATA IN level, node B will tend to rise as TM2 charges CS2 (CS2 represents the parasitic capacitance of all elements attached to node B). If TM2 is a lower power device (low width to length ratio), the current into node B will take a long time to bring that node positive, and since output transistor TO4 is a source follower, the output transition will be undesirably prolonged.

Conventionally, this problem would be overcome by increasing the size of TM1 and TM2, to allow larger charging currents, but then this would tend to increase the level of current drawn by the aggregate circuit in the standby condition (i.e., between writing operations). It may be noted, however, that if sources of charging current could be switched into nodes A and B only during transitional writing o...