Browse Prior Art Database

Floating Point Operand Normalization

IP.com Disclosure Number: IPCOM000050980D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Finney, DW: AUTHOR [+2]

Abstract

A microprogram-controlled circuit is described which will normalize floating point operands efficiently, using as few microwords and execution cycles as possible. Floating point operands must be stored in normalized format. This requires that the high-order hexadecimal digit of the fraction be nonzero. However, after most floating point operations, it is possible to have one or more high-order zeros in the fraction. The fraction must be shifted left until there is no hexadecimal zero in the high-order position and a characteristic minus one operation must be performed for each digit shifted out. The hardware shown in the figure assists the microprogram in shifting out the zero digits and updating the characteristic.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 82% of the total text.

Page 1 of 2

Floating Point Operand Normalization

A microprogram-controlled circuit is described which will normalize floating point operands efficiently, using as few microwords and execution cycles as possible. Floating point operands must be stored in normalized format. This requires that the high-order hexadecimal digit of the fraction be nonzero. However, after most floating point operations, it is possible to have one or more high-order zeros in the fraction. The fraction must be shifted left until there is no hexadecimal zero in the high-order position and a characteristic minus one operation must be performed for each digit shifted out. The hardware shown in the figure assists the microprogram in shifting out the zero digits and updating the characteristic.

The characteristic of the operand is stored in a seven-bit register 1 which is coupled to an arithmetic and logic unit (ALU) 2. The fraction A is stored in a sixty- bit shift register 3 which is capable of being shifted left four bits (one hexadecimal digit) during the execution of each microword if the four high-order bits of the fraction are zero. The four high-order bits of 3 are ORed together at 4 to determine if the high-order hexadecimal digit is zero or nonzero (any bit "on" indicates nonzero). When the microprogram control "normalize operand" is issued at 5 and the output 6 is zero, then shift register controls 7 will be activated to shift A left one hexadecimal digit within 3. Also, controls 8 will be acti...