Browse Prior Art Database

Electronic Cache Memory for Processor

IP.com Disclosure Number: IPCOM000050981D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Baker, ED: AUTHOR [+2]

Abstract

An attachment card, together with programming, eliminates the constraints of restricted addressing on 4 processor. A processor, such as the IBM Series/1 processor, provides attachment features which allow the user to attach input/output (I/O) devices and equipment to an IBM 4953 or 4955 processor, the latter being illustrated in the drawing as block 1. Block 1 includes a central processing unit 2, console 3, storage 4, optional relocation translator 5 and channel 6. Individual tasks generate addresses within the task itself ; the relocation translator then maps the tasks into actual storage 4 hardware addresses. The Series/1 offers the single channel 6 to which all input/output devices are interfaced including special processors like the floating-point feature 7.

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Electronic Cache Memory for Processor

An attachment card, together with programming, eliminates the constraints of restricted addressing on 4 processor. A processor, such as the IBM Series/1 processor, provides attachment features which allow the user to attach input/output (I/O) devices and equipment to an IBM 4953 or 4955 processor, the latter being illustrated in the drawing as block 1. Block 1 includes a central processing unit 2, console 3, storage 4, optional relocation translator 5 and channel 6. Individual tasks generate addresses within the task itself ; the relocation translator then maps the tasks into actual storage 4 hardware addresses. The Series/1 offers the single channel 6 to which all input/output devices are interfaced including special processors like the floating-point feature
7. The attachment features, such as block 8 with attached I/O device 9, communicate directly with the CPU 2 via the processor I/O channel 6.

An expansion unit 11 may be attached to support up to 13 additional feature cards (and I/O devices). Such a unit would ordinarily have a repower card to provide adequate power and isolation.

An additional attachment card 12 serves as an electronic cache memory. This card, while conforming to Series/1 I/O architecture, is attached to no I/O devices. Instead, it has up to 16 megabytes of on-board random-access memory.

As background, a device control block (DCB) is used for cycle steal operations involving I/O devices. The DCB is an eight-word control block residing in the supervisor area of storage 4. It contains the specific parameters of a cycle steal operation. An I/O device fetches the DCB using a cycle steal mechanism.

An immediate device control block (IDCB) contains an I/O command that describes the specific nature of an I/O operation. This command is used by the channel for execution of the operation.

Using a 24-bit address in the device control block, the user may read or write data to attachment card 12 in even byte quantities up to 64K bytes per device control block. DCB chaining is supported. The software to support card 12 provides the following functions: transient swapping, program c...