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Circular Priority Circuit

IP.com Disclosure Number: IPCOM000050983D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Kelley, RA: AUTHOR

Abstract

A circular priority circuit is described that insures service for each of a number of incoming requests independently of the combined rate of all other requests. This is similar in function to a rotating priority circuit, but requires less circuits for a large number of independent requests. The point where a circular priority circuit becomes more efficient depends on the technology used.

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Circular Priority Circuit

A circular priority circuit is described that insures service for each of a number of incoming requests independently of the combined rate of all other requests. This is similar in function to a rotating priority circuit, but requires less circuits for a large number of independent requests. The point where a circular priority circuit becomes more efficient depends on the technology used.

An eight-bit rotating priority circuit can be constructed in several ways. When the primary circuit is a programmable logic array (PLA), the PLA will have eleven inputs, sixty-four product terms and eight outputs. The number of product terms will be equal to the square of the number of requests. Logic gates on the inputs and outputs of an eight-bit linear priority circuit will provide an identical function. The number of logic gates required will be two times the square of the number of requests. A read-only storage can be used also. The number of storage cells required is 2 raised to the power of N, which represents the number of requests plus the log to the base 2 of N.

A block diagram of the circular priority circuit is shown in

Fig. 1. The request inputs (REQ) 1 set bits in a request register 2.

A linear priority circuit 3 determines the highest priority active request and sets the corresponding bit in an acknowledge register 4 which provides acknowledge (ACK) signals. An inhibit control block 5 monitors the request register and linear priority circuit outputs.

When a request register bit is set and there is no corresponding acknowledge out of the linear priority circuit, then more...