Browse Prior Art Database

Source Equals IAR Plus 2

IP.com Disclosure Number: IPCOM000050986D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Hardin, DK: AUTHOR [+2]

Abstract

An IBM Series/1 processor is provided with an instruction address register (IAR) that incorporates hardware to derive an IAR+2 value rather than making use of the A register and the arithmetic logic unit (ALU) as done heretofore, thus saving one machine cycle.

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Source Equals IAR Plus 2

An IBM Series/1 processor is provided with an instruction address register (IAR) that incorporates hardware to derive an IAR+2 value rather than making use of the A register and the arithmetic logic unit (ALU) as done heretofore, thus saving one machine cycle.

IAR+2 is frequently used in the branch instruction microcode to point at the address of the next I-stream word without actually incrementing the IAR first. This is important because in this processor, incrementing the IAR initiates a pre- I-fetch to bring another word into the instruction buffer, but this word would be invalid if a branch were about to occur.

The drawing shows the IAR 1 and a +2 incrementor 2 feeding the processor bus funnel 3. This incrementor saves a cycle over the previous processor which transferred the IAR to the A register 4 in one cycle and the ALU 5 output to the processor bus in a second cycle.

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