Browse Prior Art Database

Native Clock Integrity for Burst Mode Operations

IP.com Disclosure Number: IPCOM000050988D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Jones, JF: AUTHOR [+3]

Abstract

A processor Native Clock feature is incremented by microcode control. A condition exists when the channel is in burst mode operation that the microcode can be locked up waiting for the channel to respond and this is resolved by the scheme described here.

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Native Clock Integrity for Burst Mode Operations

A processor Native Clock feature is incremented by microcode control. A condition exists when the channel is in burst mode operation that the microcode can be locked up waiting for the channel to respond and this is resolved by the scheme described here.

An IBM Model 4954 Series/1 processor is provided with a Native Clock feature. The clock is a single 32-bit register which is incremented at approximately one-millisecond intervals. The processor contains a hardware timer which posts a clock interrupt to the microcode every millisecond. The microcode services the interrupt by adding one to the clock register and clearing the hardware interrupt. If the interrupt is not serviced within a millisecond, a hardware timer overrun occurs and a central processing unit (CPU) control check is produced.

In executing the priority interrupt microcode routine, a request will be made to the channel to fetch the interrupt identification and load it in the storage data register. If, when the microcode initiates this request, the channel is in burst mode operation, the channel will stop execution of microcode. Execution of microcode will resume when burst mode operation finishes and the interrupt identification can be fetched. Since the length of burst mode operation is indeterminate, a hardware timer overrun can result while the microcode is stopped.

A solution to this problem is to provide a microcode branch that determines if the channel is in burst mode and that postpones the fetch of the priority interrupt until burst mode is off. When the microcode enters the priority interrupt routine, a microinstruction, referred to as "Block Cycle Steal Polling," blocks the channel from starting a cycle steal poll which could result in the channel going into burst mode operation. On completion of the priority interrupt routine, the microcode will restart cycle steal polling by executing the "Allow Cycle Steal Polling" command.

Fig. 1 shows the hardware involved. The Block Cycle Steal Polling input on line 1 sets latch 2. This conditions block 3, designated Block Starting New Cycle Steal Polls, which provides an input to the Cycle Steal Polling Mechanism block
4. Outputs of latch 2 and block 4 through AND nd circuit 5 und...