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Signal Detection Circuit for Peer to Peer Rings

IP.com Disclosure Number: IPCOM000050991D
Original Publication Date: 1982-Dec-01
Included in the Prior Art Database: 2005-Feb-10
Document File: 4 page(s) / 42K

Publishing Venue

IBM

Related People

Couden, DV: AUTHOR [+2]

Abstract

In a peer to peer data communication ring suggested in Fig. 1, stations 2 have data processing and storage equipment which enable them to examine the information content of signals received from preceding stations on the ring 3, to accept and store signals having local destinations and to forward signals having other destinations (as well as local origin signals) to succeeding stations.

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Signal Detection Circuit for Peer to Peer Rings

In a peer to peer data communication ring suggested in Fig. 1, stations 2 have data processing and storage equipment which enable them to examine the information content of signals received from preceding stations on the ring 3, to accept and store signals having local destinations and to forward signals having other destinations (as well as local origin signals) to succeeding stations.

In this environment, it is necessary for each station to be able to determine when its incoming signals represent non-meaningful data, and when such error conditions are other than very short term noise or transmission disturbances, to be able to take action to isolate the respective station from the ring while transferring incoming ring traffic directly between station receiving and transmitting ports so as to provide continuity between preceding and succeeding stations.

The circuit shown in Fig. 2 permits the stations to carry out such error detection and reconfiguration operations. This circuit monitors the received data and the clock signal which is derived from it by the receiver s clock extraction circuit. The circuit checks for the continuous presence of the extracted clock signals, as well as ensuring that the data stream represents error-free Manchester encoding. Strings of three or more clock periods without a data signal transition represent deviations from properly encoded data. Detecting these conditions can determine if incoming data stream represents a sequence of invalid bits. The outputs of the detect circuitry may be used to drive a pair of light-emitting diode (LED) displays to give a visual indication of the operation of the unit during normal and diagnostic operation. The output of the detect circuit can also be used to control interconnections between reception and transmission circuits in the associated station, for placing station processing circuits relative to ring 3.

Specifically, D-type flip-flops FF1, FF2 and FF3, connected as a 3-bit shift register, monitor the last three bits in the received data stream with reference to the derived clock having a nominal 4 MHz frequency. Manchester encoding requires two clocking time slots for each data bit transmitted, and at least one level transition per bit. Therefore, clocking of the same level into this shift register during three consecutive clock periods represents a code violation. NAND gates 10 and 12 detect this condition relative to complementary outputs of the register flip-flops.

The detection circuit above will not function properly if it does not receive a consistent clock from the clock extraction circuit (a valid set of states may be latched into the flip-flops, and with the absence of a clock, a data input which does not change at all might go undetected). D-type flip-flops FF4, FF5 and FF6 and gate 14 check for the presence of this clock to eliminate possible invalid signal conditions which would otherwise be ignored...